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Wed, 11 Sep 2019 06:39:20 +0000 From: To: , , , , , CC: , Subject: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL Thread-Topic: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL Thread-Index: AQHVaGukjPTRbry/ckGMFC3Lf3IeQA== Date: Wed, 11 Sep 2019 06:39:20 +0000 Message-ID: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR0102CA0082.eurprd01.prod.exchangelabs.com (2603:10a6:803:15::23) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-mailer: git-send-email 2.7.4 x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 25e91481-975b-48a5-f39b-08d73682c698 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:DM5PR11MB1946; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 25e91481-975b-48a5-f39b-08d73682c698 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Sep 2019 06:39:20.5203 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: U9RDofPCMYAAgsTdjxP8E6utXaEb4WaImlmiKP/LNfa1nvTL6JuM92jz5tn33R/7DPDRrM7to4pirNKRqGaihmDyAibbkeJp8DASKburk+0= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR11MB1946 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Eugen Hristev The PLL input range needs to be able to allow 24 Mhz crystal as input Update the range accordingly in plla characteristics struct Signed-off-by: Eugen Hristev --- drivers/clk/at91/sama5d2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index 6509d09..0de1108 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] =3D { }; =20 static const struct clk_pll_characteristics plla_characteristics =3D { - .input =3D { .min =3D 12000000, .max =3D 12000000 }, + .input =3D { .min =3D 12000000, .max =3D 24000000 }, .num_output =3D ARRAY_SIZE(plla_outputs), .output =3D plla_outputs, .icpll =3D plla_icpll, --=20 2.7.4