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From:   <Nicolas.Ferre@microchip.com>
To:     <Eugen.Hristev@microchip.com>, <mturquette@baylibre.com>,
        <sboyd@kernel.org>, <alexandre.belloni@bootlin.com>,
        <linux-clk@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Thread-Topic: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Thread-Index: AQHVaGukjPTRbry/ckGMFC3Lf3IeQKcmC9UA
Date:   Wed, 11 Sep 2019 07:03:08 +0000
Message-ID: <0e8083a3-9443-e2f0-d4a3-1b02a5728759@microchip.com>
References: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com>
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On 11/09/2019 at 08:39, Eugen Hristev - M18282 wrote:
> From: Eugen Hristev <eugen.hristev@microchip.com>
>=20
> The PLL input range needs to be able to allow 24 Mhz crystal as input
> Update the range accordingly in plla characteristics struct
>=20
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>

Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Thanks Eugen!

Best regards,
   Nicolas

> ---
>   drivers/clk/at91/sama5d2.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>=20
> diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
> index 6509d09..0de1108 100644
> --- a/drivers/clk/at91/sama5d2.c
> +++ b/drivers/clk/at91/sama5d2.c
> @@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] =3D {
>   };
>  =20
>   static const struct clk_pll_characteristics plla_characteristics =3D {
> -	.input =3D { .min =3D 12000000, .max =3D 12000000 },
> +	.input =3D { .min =3D 12000000, .max =3D 24000000 },
>   	.num_output =3D ARRAY_SIZE(plla_outputs),
>   	.output =3D plla_outputs,
>   	.icpll =3D plla_icpll,
>=20


--=20
Nicolas Ferre