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From:   Alexander Dahl <ada@thorsis.com>
To:     linux-arm-kernel@lists.infradead.org
Cc:     Eugen.Hristev@microchip.com, mturquette@baylibre.com,
        sboyd@kernel.org, alexandre.belloni@bootlin.com,
        linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL
Date:   Thu, 12 Sep 2019 13:06:20 +0200
Message-ID: <30755021.BkS3ObC0RA@ada>
In-Reply-To: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com>
References: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com>
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Hello, 

out of curiosity: The SAMA5D27-SOM1-EK board has a 24 MHz crystal, that is 
also what /sys/kernel/debug/clk/clk_summary says and the board runs without 
obvious problems. What is this change improving in real practice then?

Greets
Alex

Am Mittwoch, 11. September 2019, 06:39:20 CEST schrieb 
Eugen.Hristev@microchip.com:
> From: Eugen Hristev <eugen.hristev@microchip.com>
> 
> The PLL input range needs to be able to allow 24 Mhz crystal as input
> Update the range accordingly in plla characteristics struct
> 
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> ---
>  drivers/clk/at91/sama5d2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
> index 6509d09..0de1108 100644
> --- a/drivers/clk/at91/sama5d2.c
> +++ b/drivers/clk/at91/sama5d2.c
> @@ -21,7 +21,7 @@ static const struct clk_range plla_outputs[] = {
>  };
> 
>  static const struct clk_pll_characteristics plla_characteristics = {
> -	.input = { .min = 12000000, .max = 12000000 },
> +	.input = { .min = 12000000, .max = 24000000 },
>  	.num_output = ARRAY_SIZE(plla_outputs),
>  	.output = plla_outputs,
>  	.icpll = plla_icpll,