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Thu, 12 Sep 2019 11:28:00 +0000 From: To: , CC: , , , , Subject: Re: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL Thread-Topic: [PATCH] clk: at91: allow 24 Mhz clock as input for PLL Thread-Index: AQHVaGukjPTRbry/ckGMFC3Lf3IeQKcn414AgAAEhwA= Date: Thu, 12 Sep 2019 11:28:00 +0000 Message-ID: References: <1568183622-7858-1-git-send-email-eugen.hristev@microchip.com> <30755021.BkS3ObC0RA@ada> In-Reply-To: <30755021.BkS3ObC0RA@ada> Accept-Language: en-US, ro-RO Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR08CA0210.eurprd08.prod.outlook.com (2603:10a6:802:15::19) To DM5PR11MB1242.namprd11.prod.outlook.com (2603:10b6:3:14::8) x-ms-exchange-messagesentrepresentingtype: 1 x-tagtoolbar-keys: D20190912142232678 x-originating-ip: [94.177.32.156] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: d0016782-c69f-4fe0-8aeb-08d7377444c0 x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600166)(711020)(4605104)(1401327)(2017052603328)(7193020);SRVR:DM5PR11MB1417; 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