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[216.228.112.22]) by smtp.gmail.com with ESMTPSA id u5sm27193129pfl.25.2019.09.12.16.51.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 12 Sep 2019 16:51:25 -0700 (PDT) Date: Thu, 12 Sep 2019 16:51:03 -0700 From: Nicolin Chen To: "S.j. Wang" Cc: "timur@kernel.org" , "Xiubo.Lee@gmail.com" , "festevam@gmail.com" , "lgirdwood@gmail.com" , "broonie@kernel.org" , "perex@perex.cz" , "tiwai@suse.com" , "alsa-devel@alsa-project.org" , "linuxppc-dev@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 2/3] ASoC: fsl_asrc: update supported sample format Message-ID: <20190912235103.GD24937@Asurada-Nvidia.nvidia.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Sep 10, 2019 at 02:07:25AM +0000, S.j. Wang wrote: > > On Mon, Sep 09, 2019 at 06:33:20PM -0400, Shengjiu Wang wrote: > > > The ASRC support 24bit/16bit/8bit input width, so S20_3LE format > > > should not be supported, it is word width is 20bit. > > > > I thought 3LE used 24-bit physical width. And the driver assigns > > ASRC_WIDTH_24_BIT to "width" for all non-16bit cases, so 20-bit would go > > for that 24-bit slot also. I don't clearly recall if I had explicitly tested > > S20_3LE, but I feel it should work since I put there... > > For S20_3LE, the width is 20bit, but the ASRC only support 24bit, if set the > ASRMCR1n.IWD= 24bit, because the actual width is 20 bit, the volume is > Lower than expected, it likes 24bit data right shift 4 bit. > So it is not supported. Hmm..S20_3LE right-aligns 20 bits in a 24-bit slot? I thought they're left aligned... If this is the case...shouldn't we have the same lower-volume problem for all hardwares that support S20_3LE now?