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Fri, 13 Sep 2019 19:00:56 +0000 From: "Suthikulpanit, Suravee" To: "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" CC: "pbonzini@redhat.com" , "rkrcmar@redhat.com" , "joro@8bytes.org" , "vkuznets@redhat.com" , "graf@amazon.com" , "jschoenh@amazon.de" , "karahmed@amazon.de" , "rimasluk@amazon.com" , "Grimm, Jon" , "Suthikulpanit, Suravee" Subject: [PATCH v3 06/16] kvm: x86: svm: Add support to activate/deactivate posted interrupts Thread-Topic: [PATCH v3 06/16] kvm: x86: svm: Add support to activate/deactivate posted interrupts Thread-Index: AQHVamWS7aEJ/uHZSEquRMsBUfXUeg== Date: Fri, 13 Sep 2019 19:00:56 +0000 Message-ID: <1568401242-260374-7-git-send-email-suravee.suthikulpanit@amd.com> References: <1568401242-260374-1-git-send-email-suravee.suthikulpanit@amd.com> In-Reply-To: <1568401242-260374-1-git-send-email-suravee.suthikulpanit@amd.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [165.204.78.1] x-clientproxiedby: SN6PR08CA0021.namprd08.prod.outlook.com (2603:10b6:805:66::34) To DM6PR12MB2844.namprd12.prod.outlook.com (2603:10b6:5:45::32) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Suravee.Suthikulpanit@amd.com; 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received-spf: None (protection.outlook.com: amd.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Je/+73RHpfNQnSQiFsviJkLpsEkNFx9dwFBiufkDBA7HOy3bGMfWbQXjbwouHlzI813LlFMIm1GZjKbviRg4LpqaeAQtlc+YnueIZa6/pPcAuDfxphBnTshhgYqeTFUXUtrijUupVDNLzJPiMQOpPUl2SysyiruXrM54yNs0JzT6ddQU2FavI7ZrK7OwWAKSxJ+DoGfI1ioBESUmqjLsZk2HeFCtWFoQOGZqDNYTlXc7qGj86xg9HJmXsyyEDWB9UmK4vVoFfzeiv/0RMvRs3/+2TunlE0LmROOGWIdEKVrqca0waubhForSpbraop+AKc9I7ZUEaowPiurZclUAKf1NajqyHxqHvVSykISsECibLeePXAqKr/WkadBotR63ECXfFais52cxkecnvOyiMhqbUtPPTTEKP7ncaLwrenE= Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9883ea0b-6bf4-47a8-56c5-08d7387cb528 X-MS-Exchange-CrossTenant-originalarrivaltime: 13 Sep 2019 19:00:56.6402 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0Gg5O7rkNMKkOexJZoqKBhZyOjQLRqZFU7rBPcC1b00O59fIOUWh7CcZFcuhpIHZ0l+57nEQTgzh5FkuoBD/CA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3804 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Introduce interface for activate/deactivate posted interrupts, and implement SVM hooks to toggle AMD IOMMU guest virtual APIC mode. Signed-off-by: Suravee Suthikulpanit --- arch/x86/include/asm/kvm_host.h | 4 ++++ arch/x86/kvm/svm.c | 44 +++++++++++++++++++++++++++++++++++++= ++++ arch/x86/kvm/x86.c | 5 +++++ 3 files changed, 53 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_hos= t.h index a50fca1b..624e883 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1193,6 +1193,10 @@ struct kvm_x86_ops { =20 int (*update_pi_irte)(struct kvm *kvm, unsigned int host_irq, uint32_t guest_irq, bool set); + + int (*activate_pi_irte)(struct kvm_vcpu *vcpu); + int (*deactivate_pi_irte)(struct kvm_vcpu *vcpu); + void (*apicv_post_state_restore)(struct kvm_vcpu *vcpu); bool (*dy_apicv_has_pending_interrupt)(struct kvm_vcpu *vcpu); =20 diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c index 245bde0..8673617 100644 --- a/arch/x86/kvm/svm.c +++ b/arch/x86/kvm/svm.c @@ -5398,6 +5398,48 @@ static int svm_update_pi_irte(struct kvm *kvm, unsig= ned int host_irq, return ret; } =20 +static int svm_set_pi_irte_mode(struct kvm_vcpu *vcpu, bool activate) +{ + int ret =3D 0; + unsigned long flags; + struct amd_svm_iommu_ir *ir; + struct vcpu_svm *svm =3D to_svm(vcpu); + + if (!kvm_arch_has_assigned_device(vcpu->kvm)) + return 0; + + /* + * Here, we go through the per-vcpu ir_list to update all existing + * interrupt remapping table entry targeting this vcpu. + */ + spin_lock_irqsave(&svm->ir_list_lock, flags); + + if (list_empty(&svm->ir_list)) + goto out; + + list_for_each_entry(ir, &svm->ir_list, node) { + if (activate) + ret =3D amd_iommu_activate_guest_mode(ir->data); + else + ret =3D amd_iommu_deactivate_guest_mode(ir->data); + if (ret) + break; + } +out: + spin_unlock_irqrestore(&svm->ir_list_lock, flags); + return ret; +} + +static int svm_activate_pi_irte(struct kvm_vcpu *vcpu) +{ + return svm_set_pi_irte_mode(vcpu, true); +} + +static int svm_deactivate_pi_irte(struct kvm_vcpu *vcpu) +{ + return svm_set_pi_irte_mode(vcpu, false); +} + static int svm_nmi_allowed(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); @@ -7321,6 +7363,8 @@ static bool svm_need_emulation_on_page_fault(struct k= vm_vcpu *vcpu) .deliver_posted_interrupt =3D svm_deliver_avic_intr, .dy_apicv_has_pending_interrupt =3D svm_dy_apicv_has_pending_interrupt, .update_pi_irte =3D svm_update_pi_irte, + .activate_pi_irte =3D svm_activate_pi_irte, + .deactivate_pi_irte =3D svm_deactivate_pi_irte, .setup_mce =3D svm_setup_mce, =20 .smi_allowed =3D svm_smi_allowed, diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index bc74876..1540629 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -7198,6 +7198,9 @@ void kvm_vcpu_activate_apicv(struct kvm_vcpu *vcpu) kvm_apic_update_apicv(vcpu); =20 kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); + + if (kvm_x86_ops->activate_pi_irte) + kvm_x86_ops->activate_pi_irte(vcpu); } EXPORT_SYMBOL_GPL(kvm_vcpu_activate_apicv); =20 @@ -7212,6 +7215,8 @@ void kvm_vcpu_deactivate_apicv(struct kvm_vcpu *vcpu) =20 vcpu->arch.apicv_active =3D false; kvm_apic_update_apicv(vcpu); + if (kvm_x86_ops->deactivate_pi_irte) + kvm_x86_ops->deactivate_pi_irte(vcpu); kvm_x86_ops->refresh_apicv_exec_ctrl(vcpu); } EXPORT_SYMBOL_GPL(kvm_vcpu_deactivate_apicv); --=20 1.8.3.1