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Date:   Wed, 18 Sep 2019 13:08:48 +0100
From:   Mark Brown <broonie@kernel.org>
To:     "Ramuthevar, Vadivel MuruganX" 
        <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc:     robh+dt@kernel.org, mark.rutland@arm.com,
        linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, cheol.yong.kim@intel.com,
        qi-ming.wu@intel.com
Subject: Re: [PATCH v1 2/2] spi: cadence-qspi: Add QSPI support for Intel LGM
 SoC
Message-ID: <20190918120846.GH2596@sirena.co.uk>
References: <20190916073843.39618-1-vadivel.muruganx.ramuthevar@linux.intel.com>
 <20190916073843.39618-3-vadivel.muruganx.ramuthevar@linux.intel.com>
 <20190916113255.GA4352@sirena.co.uk>
 <466b41c1-3d65-0bf4-6db7-d3b3e06b107b@linux.intel.com>
 <20190917153650.GF3524@sirena.co.uk>
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On Wed, Sep 18, 2019 at 01:59:06PM +0800, Ramuthevar, Vadivel MuruganX wrot=
e:
> On 17/9/2019 11:36 PM, Mark Brown wrote:
> > On Tue, Sep 17, 2019 at 10:11:28AM +0800, Ramuthevar, Vadivel MuruganX =
wrote:

> > > *=A0=A0=A0 spi-cadence.c* in *drivers/spi/*, which supports very old =
legacy
> > > cadence-spi based devices(normal)
> > > *=A0=A0=A0 cadence-quadspi.c(drivers/mtd/spi-nor/)* : specific suppor=
t to SPI-NOR
> > > flash with new spi-nor layer.
> > >  =A0=A0=A0 all the API's in this driver purely on spi-nor specific, s=
o couldn't
> > > proceed to adapt.

> > Are these completely separate IPs or are they just different versions of
> > the same IP?

> These are same IPs , but different features Enabled/Disabled depends upon
> the SoC vendors.

> for e.g: Intel LGM SoC uses the same IP, but without DMA and Direct access
> controller.

> also dedicated support to flash devices.

If it's different versions of the same IP then everything should be in
one driver with the optional features enabled depending on what's in a
given system.

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