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[209.132.180.67]) by mx.google.com with ESMTP id o26si3113869ejr.148.2019.09.18.09.44.26; Wed, 18 Sep 2019 09:44:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731044AbfIRMY6 (ORCPT + 99 others); Wed, 18 Sep 2019 08:24:58 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:22187 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731006AbfIRMY5 (ORCPT ); Wed, 18 Sep 2019 08:24:57 -0400 X-UUID: 76427532d0cd4e409641ba6cfc6e3454-20190918 X-UUID: 76427532d0cd4e409641ba6cfc6e3454-20190918 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1610868906; Wed, 18 Sep 2019 20:24:44 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33DR.mediatek.inc (172.27.6.106) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 18 Sep 2019 20:24:40 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (172.27.4.253) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 18 Sep 2019 20:24:39 +0800 From: Jitao Shi To: Sam Ravnborg , David Airlie , "Daniel Vetter" , , CC: , , , , , , , , Jitao Shi Subject: [PATCH v6 4/8] drm/panel: support for auo,kd101n80-45na wuxga dsi video mode panel Date: Wed, 18 Sep 2019 20:24:18 +0800 Message-ID: <20190918122422.17339-5-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190918122422.17339-1-jitao.shi@mediatek.com> References: <20190918122422.17339-1-jitao.shi@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Content-Type: text/plain; charset=US-ASCII X-TM-AS-Product-Ver: SMEX-12.5.0.1684-8.5.1010-24918.004 X-TM-AS-Result: No-5.342400-8.000000-10 X-TMASE-MatchedRID: lYyMbP31ZgbQIwAe9yDqC/3HILfxLV/9NV9S7O+u3Kax6d2WO4Kt3WMg VHfStGn6oODj/ed0fo2pXR7NA6GzIq0iin8P0KjVPwKTD1v8YV5MmIwvtVXGIkp12IXZajx5ZDK 4bzNNBeUyPUKH+39d75mQE0Q29MHfk4P+vqTbTVFJkkUW0nPbN/G6GRFYrbYYVWQnHKxp38gKJ5 OVHpTWmhkNsHcU+86WQxx/Lw6+Y+7ZD1adyQZ2PvKUR83BvqItiK5qg1cmsr+sTiwQDTUmaQYxJ ykfuo4ABZ3DASds/MqZ5OJl4gE/ShgHZ8655DOPFEUknJ/kEl7dB/CxWTRRu25FeHtsUoHuaBkD YFryyQrVTvo1TO59OOMFE88M2XK9UIS5qWo+0Nu+68HqACCvKA== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--5.342400-8.000000 X-TMASE-Version: SMEX-12.5.0.1684-8.5.1010-24918.004 X-TM-SNTS-SMTP: 8D623F33BA85C518BFB65A5DDC71C7409DE4248BE5DACD458AA82622C59775F72000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Auo,kd101n80-45na's connector is same as boe,tv101wum-nl6. The most codes can be reuse. So auo,kd101n80-45na and boe,tv101wum-nl6 use one driver file. Add the different parts in driver data. Signed-off-by: Jitao Shi --- drivers/gpu/drm/panel/Kconfig | 6 +- .../gpu/drm/panel/panel-boe-tv101wum-nl6.c | 86 ++++++++++++++++--- 2 files changed, 75 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/panel/Kconfig b/drivers/gpu/drm/panel/Kconfig index afcadb3585fb..0e887c978796 100644 --- a/drivers/gpu/drm/panel/Kconfig +++ b/drivers/gpu/drm/panel/Kconfig @@ -19,13 +19,13 @@ config DRM_PANEL_ARM_VERSATILE in the Versatile family syscon registers. config DRM_PANEL_BOE_TV101WUM_NL6 - tristate "BOE TV101WUM 1200x1920 panel" + tristate "BOE TV101WUM and AUO KD101N80 45NA 1200x1920 panel" depends on OF depends on DRM_MIPI_DSI depends on BACKLIGHT_CLASS_DEVICE help - Say Y here if you want to support for BOE TV101WUM WUXGA PANEL - DSI Video Mode panel + Say Y here if you want to support for BOE TV101WUM and AUO KD101N80 + 45NA WUXGA PANEL DSI Video Mode panel config DRM_PANEL_LVDS tristate "Generic LVDS panel driver" diff --git a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c index e27529b80d78..f80974778360 100644 --- a/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c +++ b/drivers/gpu/drm/panel/panel-boe-tv101wum-nl6.c @@ -35,6 +35,7 @@ struct panel_desc { enum mipi_dsi_pixel_format format; const struct panel_init_cmd *init_cmds; unsigned int lanes; + bool discharge_on_disable; }; struct boe_panel { @@ -372,6 +373,15 @@ static const struct panel_init_cmd boe_init_cmd[] = { {}, }; +static const struct panel_init_cmd auo_kd101n80_45na_init_cmd[] = { + _INIT_DELAY_CMD(24), + _INIT_DCS_CMD(0x11), + _INIT_DELAY_CMD(120), + _INIT_DCS_CMD(0x29), + _INIT_DELAY_CMD(120), + {}, +}; + static inline struct boe_panel *to_boe_panel(struct drm_panel *panel) { return container_of(panel, struct boe_panel, base); @@ -449,20 +459,30 @@ static int boe_panel_unprepare(struct drm_panel *panel) if (!boe->prepared) return 0; - ret = boe_panel_off(boe); - if (ret < 0) { - dev_err(panel->dev, "failed to set panel off: %d\n", ret); - return ret; + if (boe->desc->discharge_on_disable) { + msleep(150); + regulator_disable(boe->avee); + regulator_disable(boe->avdd); + usleep_range(5000, 7000); + gpiod_set_value(boe->enable_gpio, 0); + usleep_range(5000, 7000); + regulator_disable(boe->pp1800); + } else { + ret = boe_panel_off(boe); + if (ret < 0) { + dev_err(panel->dev, "failed to set panel off: %d\n", + ret); + return ret; + } + msleep(150); + gpiod_set_value(boe->enable_gpio, 0); + usleep_range(500, 1000); + regulator_disable(boe->avee); + regulator_disable(boe->avdd); + usleep_range(5000, 7000); + regulator_disable(boe->pp1800); } - msleep(150); - gpiod_set_value(boe->enable_gpio, 0); - usleep_range(500, 1000); - regulator_disable(boe->avee); - regulator_disable(boe->avdd); - usleep_range(5000, 7000); - regulator_disable(boe->pp1800); - boe->prepared = false; return 0; @@ -492,10 +512,14 @@ static int boe_panel_prepare(struct drm_panel *panel) if (ret < 0) goto poweroffavdd; - msleep(100); + usleep_range(5000, 10000); gpiod_set_value(boe->enable_gpio, 1); - usleep_range(10000, 12000); + usleep_range(1000, 2000); + gpiod_set_value(boe->enable_gpio, 0); + usleep_range(1000, 2000); + gpiod_set_value(boe->enable_gpio, 1); + usleep_range(6000, 10000); ret = boe_panel_init(boe); if (ret < 0) { @@ -527,6 +551,8 @@ static int boe_panel_enable(struct drm_panel *panel) if (boe->enabled) return 0; + msleep(70); + ret = backlight_enable(boe->backlight); if (ret) { dev_err(panel->dev, "Failed to enable backlight %d\n", @@ -564,6 +590,35 @@ static const struct panel_desc boe_tv101wum_nl6_desc = { .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM, .init_cmds = boe_init_cmd, + .discharge_on_disable = false, +}; + +static const struct drm_display_mode auo_kd101n80_45na_default_mode = { + .clock = 157000, + .hdisplay = 1200, + .hsync_start = 1200 + 80, + .hsync_end = 1200 + 80 + 24, + .htotal = 1200 + 80 + 24 + 36, + .vdisplay = 1920, + .vsync_start = 1920 + 16, + .vsync_end = 1920 + 16 + 4, + .vtotal = 1920 + 16 + 4 + 16, + .vrefresh = 60, +}; + +static const struct panel_desc auo_kd101n80_45na_desc = { + .modes = &auo_kd101n80_45na_default_mode, + .bpc = 8, + .size = { + .width_mm = 135, + .height_mm = 216, + }, + .lanes = 4, + .format = MIPI_DSI_FMT_RGB888, + .mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM, + .init_cmds = auo_kd101n80_45na_init_cmd, + .discharge_on_disable = true, }; static int boe_panel_get_modes(struct drm_panel *panel) @@ -689,6 +744,9 @@ static const struct of_device_id boe_of_match[] = { { .compatible = "boe,tv101wum-nl6", .data = &boe_tv101wum_nl6_desc }, + { .compatible = "auo,kd101n80-45na", + .data = &auo_kd101n80_45na_desc + }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, boe_of_match); -- 2.21.0