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[209.132.180.67]) by mx.google.com with ESMTP id p14si5114291ejn.192.2019.09.19.07.25.40; Thu, 19 Sep 2019 07:26:04 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@hardenedlinux.org header.s=protonmail header.b=h9Meoilm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731857AbfISKa1 (ORCPT + 99 others); Thu, 19 Sep 2019 06:30:27 -0400 Received: from mail4.protonmail.ch ([185.70.40.27]:44985 "EHLO mail4.protonmail.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727980AbfISKa0 (ORCPT ); Thu, 19 Sep 2019 06:30:26 -0400 Date: Thu, 19 Sep 2019 10:30:15 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=hardenedlinux.org; s=protonmail; t=1568889022; bh=hiwcVYVyjA8rIAfDxqCw5jAP15PD6IpvcY7gJcQeLRw=; h=Date:To:From:Cc:Reply-To:Subject:In-Reply-To:References: Feedback-ID:From; b=h9MeoilmyiThRpXXIznQvZEu05WaaRsTkYkmbaIdTzRfg6CPLp0LSSTgss8sfSrBa 5JWkj7nP9SSQ/glRfXBu05XhnIf2bXK0RZSLFwPw6FlAHdKEOzuroZqhsZ6RzeQGnB Scy381WsKNTdZ18VxQT57InOO0JU2PdCrt5wOq3M= To: Paul Walmsley From: Xiang Wang Cc: "palmer@sifive.com" , "aou@eecs.berkeley.edu" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "citypw@hardenedlinux.org" Reply-To: Xiang Wang Subject: Re: [PATCH] arch/riscv: disable too many harts before pick main boot hart Message-ID: In-Reply-To: References: Feedback-ID: BRRa7Rf7LqOlikZR00e5gSr_IsihWq0drDTak4NnawY-ONQTW87vpTHz90bkJTl_rn8r4L6gc-nP1pm37CQtxw==:Ext:ProtonMail MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-1.2 required=7.0 tests=ALL_TRUSTED,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on mail.protonmail.ch Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org =E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90 Original Me= ssage =E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90=E2=80=90 On 2019=E5=B9=B49=E6=9C=8819=E6=97=A5ThursdayPM6=E7=82=B925=E5=88=86, Paul = Walmsley wrote: > On Fri, 6 Sep 2019, Xiang Wang wrote: > > > From 12300865d1103618c9d4c375f7d7fbe601b6618c Mon Sep 17 00:00:00 2001 > > From: Xiang Wang merle@hardenedlinux.org > > Date: Fri, 6 Sep 2019 11:56:09 +0800 > > Subject: [PATCH] arch/riscv: disable too many harts before pick main bo= ot hart > > These harts with id greater than or equal to CONFIG_NR_CPUS need to be = disabled. > > But pick the main Hart can choose any one. So, before pick the main har= t, you > > need to disable the hart with id greater than or equal to CONFIG_NR_CPU= S. > > Signed-off-by: Xiang Wang merle@hardenedlinux.org > > Thanks, here's what I'm planning to queue for v5.4-rc1. Please let me > know ASAP if you want to change the patch description. > > - Paul Not need to change > > From: Xiang Wang merle@hardenedlinux.org > > > Date: Fri, 6 Sep 2019 11:56:09 +0800 > Subject: [PATCH] arch/riscv: disable excess harts before picking main boo= t hart > > Harts with id greater than or equal to CONFIG_NR_CPUS need to be > disabled. But the kernel can pick any hart as the main hart. So, > before picking the main hart, the kernel must disable harts with ids > greater than or equal to CONFIG_NR_CPUS. > > Signed-off-by: Xiang Wang merle@hardenedlinux.org > Reviewed-by: Palmer Dabbelt palmer@sifive.com > [paul.walmsley@sifive.com: updated to apply; cleaned up patch > description] > Signed-off-by: Paul Walmsley paul.walmsley@sifive.com > > arch/riscv/kernel/head.S | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index 15a9189f91ad..72f89b7590dd 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -63,6 +63,11 @@ _start_kernel: > li t0, SR_FS > csrc CSR_SSTATUS, t0 > > +#ifdef CONFIG_SMP > > - li t0, CONFIG_NR_CPUS > - bgeu a0, t0, .Lsecondary_park > +#endif > > - /* Pick one hart to run the main boot sequence */ > la a3, hart_lottery > li a2, 1 > @@ -154,9 +159,6 @@ relocate: > > .Lsecondary_start: > #ifdef CONFIG_SMP > > > - li a1, CONFIG_NR_CPUS > - bgeu a0, a1, .Lsecondary_park > - /* Set trap vector to spin forever to help debug */ > la a3, .Lsecondary_park > csrw CSR_STVEC, a3 > -- > 2.23.0 >