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Thu, 19 Sep 2019 10:55:06 +0000 From: Anup Patel To: Paul Walmsley , Xiang Wang CC: "palmer@sifive.com" , "aou@eecs.berkeley.edu" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "citypw@hardenedlinux.org" Subject: RE: [PATCH] arch/riscv: disable too many harts before pick main boot hart Thread-Topic: [PATCH] arch/riscv: disable too many harts before pick main boot hart Thread-Index: AQHVZIA2865roxzFk0Oy+d+JtT78nKcy4D0AgAAH+LA= Date: Thu, 19 Sep 2019 10:55:05 +0000 Message-ID: References: In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-originating-ip: [106.51.19.133] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 27b41bd2-5434-4597-ac7f-08d73cefd4c6 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(7168020)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:MN2PR04MB6126; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: wdc.com X-MS-Exchange-CrossTenant-Network-Message-Id: 27b41bd2-5434-4597-ac7f-08d73cefd4c6 X-MS-Exchange-CrossTenant-originalarrivaltime: 19 Sep 2019 10:55:05.9685 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: b61c8803-16f3-4c35-9b17-6f65f441df86 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: tu3wczXBOCJDjwm9wNJP954907pzOxaahKPh31p184mmNk5n6w5C1EVLmvwJ0mrul+aCGHE2cAEyhaJFQeAwBg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR04MB6126 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: linux-kernel-owner@vger.kernel.org owner@vger.kernel.org> On Behalf Of Paul Walmsley > Sent: Thursday, September 19, 2019 3:56 PM > To: Xiang Wang > Cc: palmer@sifive.com; aou@eecs.berkeley.edu; linux- > riscv@lists.infradead.org; linux-kernel@vger.kernel.org; > citypw@hardenedlinux.org > Subject: Re: [PATCH] arch/riscv: disable too many harts before pick main > boot hart >=20 > On Fri, 6 Sep 2019, Xiang Wang wrote: >=20 > > From 12300865d1103618c9d4c375f7d7fbe601b6618c Mon Sep 17 00:00:00 > 2001 > > From: Xiang Wang > > Date: Fri, 6 Sep 2019 11:56:09 +0800 > > Subject: [PATCH] arch/riscv: disable too many harts before pick main > > boot hart > > > > These harts with id greater than or equal to CONFIG_NR_CPUS need to be > disabled. > > But pick the main Hart can choose any one. So, before pick the main > > hart, you need to disable the hart with id greater than or equal to > CONFIG_NR_CPUS. > > > > Signed-off-by: Xiang Wang >=20 > Thanks, here's what I'm planning to queue for v5.4-rc1. Please let me kn= ow > ASAP if you want to change the patch description. >=20 >=20 > - Paul >=20 > From: Xiang Wang > Date: Fri, 6 Sep 2019 11:56:09 +0800 > Subject: [PATCH] arch/riscv: disable excess harts before picking main boo= t > hart >=20 > Harts with id greater than or equal to CONFIG_NR_CPUS need to be > disabled. But the kernel can pick any hart as the main hart. So, > before picking the main hart, the kernel must disable harts with ids > greater than or equal to CONFIG_NR_CPUS. >=20 > Signed-off-by: Xiang Wang You missed my Reviewed-by here. Regards, Anup > Reviewed-by: Palmer Dabbelt > [paul.walmsley@sifive.com: updated to apply; cleaned up patch > description] > Signed-off-by: Paul Walmsley > --- > arch/riscv/kernel/head.S | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) >=20 > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index 15a9189f91ad..72f89b7590dd 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -63,6 +63,11 @@ _start_kernel: > li t0, SR_FS > csrc CSR_SSTATUS, t0 >=20 > +#ifdef CONFIG_SMP > + li t0, CONFIG_NR_CPUS > + bgeu a0, t0, .Lsecondary_park > +#endif > + > /* Pick one hart to run the main boot sequence */ > la a3, hart_lottery > li a2, 1 > @@ -154,9 +159,6 @@ relocate: >=20 > .Lsecondary_start: > #ifdef CONFIG_SMP > - li a1, CONFIG_NR_CPUS > - bgeu a0, a1, .Lsecondary_park > - > /* Set trap vector to spin forever to help debug */ > la a3, .Lsecondary_park > csrw CSR_STVEC, a3 > -- > 2.23.0