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[209.132.180.67]) by mx.google.com with ESMTP id g12si1177854ejw.340.2019.09.20.07.32.02; Fri, 20 Sep 2019 07:32:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405465AbfISWuj (ORCPT + 99 others); Thu, 19 Sep 2019 18:50:39 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:39564 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2389023AbfISWui (ORCPT ); Thu, 19 Sep 2019 18:50:38 -0400 X-UUID: 8b13c63bb1484e35a74513a0e03cf51e-20190920 X-UUID: 8b13c63bb1484e35a74513a0e03cf51e-20190920 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 885871584; Fri, 20 Sep 2019 06:50:31 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 20 Sep 2019 06:50:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 20 Sep 2019 06:50:26 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v9 01/11] pwm: mediatek: add a property "num-pwms" Date: Fri, 20 Sep 2019 06:49:01 +0800 Message-ID: <1568933351-8584-2-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1568933351-8584-1-git-send-email-sam.shih@mediatek.com> References: <1568933351-8584-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" to avoid having an endless list of compatibles with no differences for the same driver. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Uwe Kleine-König --- Changes since v6: Add a Reviewed-by tag Changes since v5: Check num-pwms value is no more than MTK_CLK_MAX - 2 (MAIN + TOP) Changes since v4: Follow reviewer's comments: Move the changes of droping the check for of_device_get_match_data returning non-NULL to next patch --- drivers/pwm/pwm-mediatek.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index eb6674ce995f..e214f4f57107 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -55,7 +55,7 @@ static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { }; struct mtk_pwm_platform_data { - unsigned int num_pwms; + unsigned int fallback_npwms; bool pwm45_fixup; bool has_clks; }; @@ -227,9 +227,10 @@ static const struct pwm_ops mtk_pwm_ops = { static int mtk_pwm_probe(struct platform_device *pdev) { const struct mtk_pwm_platform_data *data; + struct device_node *np = pdev->dev.of_node; struct mtk_pwm_chip *pc; struct resource *res; - unsigned int i; + unsigned int i, npwms; int ret; pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); @@ -246,7 +247,26 @@ static int mtk_pwm_probe(struct platform_device *pdev) if (IS_ERR(pc->regs)) return PTR_ERR(pc->regs); - for (i = 0; i < data->num_pwms + 2 && pc->soc->has_clks; i++) { + ret = of_property_read_u32(np, "num-pwms", &npwms); + if (ret < 0) { + /* It's deprecated, we should specify num_pwms via DT now. */ + if (pc->soc->fallback_npwms) { + npwms = pc->soc->fallback_npwms; + dev_warn(&pdev->dev, "DT is outdated, please update it\n"); + } else { + dev_err(&pdev->dev, "failed to get number of PWMs\n"); + return ret; + } + } + + /* MAIN + TOP + NPWM < MTK_CLK_MAX */ + if ((npwms + 2) > MTK_CLK_MAX) { + dev_warn(&pdev->dev, "number of PWMs is larger than %d\n", + MTK_CLK_MAX - 2); + npwms = MTK_CLK_MAX - 2; + } + + for (i = 0; i < npwms + 2 && pc->soc->has_clks; i++) { pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); if (IS_ERR(pc->clks[i])) { dev_err(&pdev->dev, "clock: %s fail: %ld\n", @@ -260,7 +280,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) pc->chip.dev = &pdev->dev; pc->chip.ops = &mtk_pwm_ops; pc->chip.base = -1; - pc->chip.npwm = data->num_pwms; + pc->chip.npwm = npwms; ret = pwmchip_add(&pc->chip); if (ret < 0) { @@ -279,25 +299,25 @@ static int mtk_pwm_remove(struct platform_device *pdev) } static const struct mtk_pwm_platform_data mt2712_pwm_data = { - .num_pwms = 8, + .fallback_npwms = 8, .pwm45_fixup = false, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7622_pwm_data = { - .num_pwms = 6, + .fallback_npwms = 6, .pwm45_fixup = false, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7623_pwm_data = { - .num_pwms = 5, + .fallback_npwms = 5, .pwm45_fixup = true, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7628_pwm_data = { - .num_pwms = 4, + .fallback_npwms = 4, .pwm45_fixup = true, .has_clks = false, }; -- 2.17.1