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References: <20190920153951.25762-1-ilie.halip@gmail.com>
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From:   Nick Desaulniers <ndesaulniers@google.com>
Date:   Fri, 20 Sep 2019 09:20:20 -0700
Message-ID: <CAKwvOdkvrRgQ7KtGag0yDH+ry7a6=pd5xudrNm9X+5oVu2Z20A@mail.gmail.com>
Subject: Re: [PATCH] powerpc/pmac/smp: avoid unused-variable warnings
To:     Ilie Halip <ilie.halip@gmail.com>
Cc:     Michael Ellerman <mpe@ellerman.id.au>,
        Nathan Chancellor <natechancellor@gmail.com>,
        clang-built-linux <clang-built-linux@googlegroups.com>,
        Benjamin Herrenschmidt <benh@kernel.crashing.org>,
        Paul Mackerras <paulus@samba.org>,
        linuxppc-dev <linuxppc-dev@lists.ozlabs.org>,
        LKML <linux-kernel@vger.kernel.org>
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On Fri, Sep 20, 2019 at 8:41 AM Ilie Halip <ilie.halip@gmail.com> wrote:
>
> When building with ppc64_defconfig, the compiler reports
> that these 2 variables are not used:
>     warning: unused variable 'core99_l2_cache' [-Wunused-variable]
>     warning: unused variable 'core99_l3_cache' [-Wunused-variable]
>
> They are only used when CONFIG_PPC64 is not defined. Move
> them into a section which does the same macro check.
>
> Reported-by: Nathan Chancellor <natechancellor@gmail.com>
> Signed-off-by: Ilie Halip <ilie.halip@gmail.com>

Hi Ilie, thanks for the patch.  LGTM (Please include link tags if your
link addresses a bug in our bug tracker; it helps us track where/when
patches land, in case they need to be backported).
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Link: https://github.com/ClangBuiltLinux/linux/issues/663

> ---
>  arch/powerpc/platforms/powermac/smp.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/platforms/powermac/smp.c b/arch/powerpc/platforms/powermac/smp.c
> index f95fbdee6efe..e44c606f119e 100644
> --- a/arch/powerpc/platforms/powermac/smp.c
> +++ b/arch/powerpc/platforms/powermac/smp.c
> @@ -648,6 +648,10 @@ static void smp_core99_pfunc_tb_freeze(int freeze)
>
>  static unsigned int core99_tb_gpio;    /* Timebase freeze GPIO */
>
> +/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
> +volatile static long int core99_l2_cache;
> +volatile static long int core99_l3_cache;
> +
>  static void smp_core99_gpio_tb_freeze(int freeze)
>  {
>         if (freeze)
> @@ -660,10 +664,6 @@ static void smp_core99_gpio_tb_freeze(int freeze)
>
>  #endif /* !CONFIG_PPC64 */
>
> -/* L2 and L3 cache settings to pass from CPU0 to CPU1 on G4 cpus */
> -volatile static long int core99_l2_cache;
> -volatile static long int core99_l3_cache;
> -
>  static void core99_init_caches(int cpu)
>  {
>  #ifndef CONFIG_PPC64
> --
> 2.17.1
>
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-- 
Thanks,
~Nick Desaulniers