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Date:   Fri, 20 Sep 2019 16:31:42 -0600
From:   Lina Iyer <ilina@codeaurora.org>
To:     Stephen Boyd <swboyd@chromium.org>
Cc:     evgreen@chromium.org, linus.walleij@linaro.org,
        marc.zyngier@arm.com, linux-kernel@vger.kernel.org,
        linux-arm-msm@vger.kernel.org, bjorn.andersson@linaro.org,
        mkshah@codeaurora.org, linux-gpio@vger.kernel.org,
        rnayak@codeaurora.org
Subject: Re: [PATCH RFC 02/14] drivers: irqchip: pdc: Do not toggle
 IRQ_ENABLE during mask/unmask
Message-ID: <20190920223142.GI15853@codeaurora.org>
References: <20190829181203.2660-1-ilina@codeaurora.org>
 <20190829181203.2660-3-ilina@codeaurora.org>
 <5d71aad9.1c69fb81.f469e.262f@mx.google.com>
 <20190911161557.GB30053@codeaurora.org>
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On Fri, Sep 20 2019 at 16:22 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-09-11 09:15:57)
>> On Thu, Sep 05 2019 at 18:39 -0600, Stephen Boyd wrote:
>> >Quoting Lina Iyer (2019-08-29 11:11:51)
>> >> When an interrupt is to be serviced, the convention is to mask the
>> >> interrupt at the chip and unmask after servicing the interrupt. Enabling
>> >> and disabling the interrupt at the PDC irqchip causes an interrupt storm
>> >> due to the way dual edge interrupts are handled in hardware.
>> >>
>> >> Skip configuring the PDC when the IRQ is masked and unmasked, instead
>> >> use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE
>> >> register at the PDC. The PDC's IRQ_ENABLE register is only used during
>> >> the monitoring mode when the system is asleep and is not needed for
>> >> active mode detection.
>> >
>> >I think this is saying that we want to always let the line be sent
>> >through the PDC to the parent irqchip, in this case GIC, so that we
>> >don't get an interrupt storm for dual edge interrupts? Why does dual
>> >edge interrupts cause a problem?
>> >
>> I am not sure about the hardware details, but the PDC designers did not
>> expect enable and disable to be called whenever the interrupt is
>> handled. This specially becomes a problem for dual edge interrupts which
>> seems to generate a interrupt storm when enabled/disabled while handling
>> the interrupt.
>>
>
>Ok. I just wanted to confirm that masking "doesn't matter" to the PDC
>because it assumes the irqchip closer to the CPU will be able to mask it
>anyway. Is that right?
>
That is correct.