Received: by 2002:a25:824b:0:0:0:0:0 with SMTP id d11csp805325ybn; Tue, 24 Sep 2019 09:46:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqwfS/GNBsSikQ73r71n0kmp7kXDq8TRJu0t9NmXCS6eRWU/O7YIX3gVPs4hN19NaoY6f39M X-Received: by 2002:a1c:6a06:: with SMTP id f6mr1145355wmc.113.1569343591447; Tue, 24 Sep 2019 09:46:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569343591; cv=none; d=google.com; s=arc-20160816; b=erFF9V/FdTExTMBNdBkIfpAu3yNdfTUASA7ov/pREo28grE16irJn+YtCrGBN7/hdK JCoyJY+D6p6skwpxeksfo8bIBrqcmXoxAX+3xoX0xZfIOclvhwL50AdFoYdZNluxrRh2 4y/nyo19pKoX1cxJ+gGa6QSavBcZSn5Eh7Yn7jDvzaDnwCy3mYrUbY3P1za1zEGa3nky mMIY/ngXYTOLMv0ivNlJGJCjAGITKLYK6EM83a7Zbgz8zjcGIwU+vIvicjpPfJpbIjPS AyqhZGloZ6o4Yb/It4Wixx73Ht6xJEXT3TFrcrYGba9ElxmX4f5b3oH4VtvLzUwz1qd7 prrQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:content-transfer-encoding :references:in-reply-to:date:cc:to:from:subject:message-id; bh=t77WeD6VZ/6owQiLVlqmTsceItPcsyLbEBNQGqNHCwI=; b=QieRkv+/DY3noG29FVOus2ixkr9TAF2Yx9URjoOUmCuWALg5OARgfiOQ0CtpftO6CY IZKYVhhlOAkFU2fTyyDjqESdBmP50D0X83roeCoPvbJAQ3stvLl5tm6nqHCK3U2uzJX1 uFTwif34YJVeaWvDqVZAoOLvoKP7RI2mfRJHSbWBWIleIAh2Vnf2xKniGyvIaMKM1/aq lOokR/Nb6p6nI6xRYXGV3fQvg10at7/RVlWExbC4JQzjnazR5PA1db2/g3gpguAiYCKR T9ZOXHvcvgTNnCY08oDnD5pNVcnm4DKPK1RrKda9iK4qAeRqgfRzJnLpTOswErPv1TB6 6gMQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 64si1743716edf.34.2019.09.24.09.46.08; Tue, 24 Sep 2019 09:46:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2405766AbfIWDVE (ORCPT + 99 others); Sun, 22 Sep 2019 23:21:04 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:16502 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2404102AbfIWDVE (ORCPT ); Sun, 22 Sep 2019 23:21:04 -0400 X-UUID: 5bbca55a9982475e99c481f9372dab08-20190923 X-UUID: 5bbca55a9982475e99c481f9372dab08-20190923 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1964829612; Mon, 23 Sep 2019 11:20:59 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 23 Sep 2019 11:20:56 +0800 Received: from [172.21.84.99] (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 23 Sep 2019 11:20:56 +0800 Message-ID: <1569208857.4102.9.camel@mtksdccf07> Subject: Re: [PATCH v9 07/11] dt-bindings: pwm: pwm-mediatek: add a property "num-pwms" From: Sam Shih To: Thierry Reding , Rob Herring CC: Mark Rutland , , "Ryder Lee" , , , , "John Crispin" , Matthias Brugger Date: Mon, 23 Sep 2019 11:20:57 +0800 In-Reply-To: <20190921002149.GB86019@mithrandir> References: <1568933351-8584-1-git-send-email-sam.shih@mediatek.com> <1568933351-8584-8-git-send-email-sam.shih@mediatek.com> <20190921002149.GB86019@mithrandir> Content-Type: text/plain; charset="ISO-8859-15" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 8bit MIME-Version: 1.0 X-TM-SNTS-SMTP: 5DE12F5DF2358BA2912DCBFA7D76065A5D51D8AAC23E3281B45386E5691BB84D2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 2019-09-21 at 02:21 +0200, Thierry Reding wrote: > On Fri, Sep 20, 2019 at 06:49:07AM +0800, Sam Shih wrote: > > From: Ryder Lee > > > > This adds a property "num-pwms" in example so that we could > > specify the number of PWM channels via device tree. > > > > Signed-off-by: Ryder Lee > > Signed-off-by: Sam Shih > > Reviewed-by: Matthias Brugger > > Acked-by: Uwe Kleine-K?nig > > --- > > Changes since v6: > > Follow reviewers's comments: > > - The subject should indicate this is for Mediatek > > > > Changes since v5: > > - Add an Acked-by tag > > - This file is original v4 patch 5/10 > > (https://patchwork.kernel.org/patch/11102577/) > > > > --- > > Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 7 ++++--- > > 1 file changed, 4 insertions(+), 3 deletions(-) > > You failed to address Rob's questions repeatedly and I agree with him > that you can just as easily derive the number of PWMs from the specific > compatible string. I won't be applying this and none of the patches that > depend on it. > Hi, Thanks for getting back to me. New pwm driver (patch 04/11 : "pwm: mediatek: allocate the clks array dynamically") can support different variants with different number of PWMs by the new property For example: 1. Use "num-pwms" = <2> and assign clocks pwm1, pwm2 for mt7622 2. Use "num-pwms" = <6> and assign clocks pwm1, pwm2, pwm3, pwm4, pwm5, pwm6 for mt7622. If we just as easily derive the number of PWMs from the specific compatible string in this document: - "pwm1-6": the six per PWM clocks for mt7622 This looks like all "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6" is required property in DT, It doesn't make sense. So we removed those descriptions and added - "pwm1-N": the PWM clocks for each channel But the max number of clocks from the compatible string are still important information that should be provide in this document. What do you think of this? - "pwm1-N": per PWM clocks for mt2712, the max number of PWM channels is 8 - "pwm1-N": per PWM clocks for mt7622, the max number of PWM channels is 6 - "pwm1-N": per PWM clocks for mt7623, the max number of PWM channels is 5 where N starting from 1 to the maximum number of PWM channels - num-pwms: the number of PWM channels. Thanks Best Regards Sam