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[209.132.180.67]) by mx.google.com with ESMTP id e48si318367eda.130.2019.09.25.16.40.24; Wed, 25 Sep 2019 16:40:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=YAC7bHog; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2502581AbfIWU0u (ORCPT + 99 others); Mon, 23 Sep 2019 16:26:50 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:2785 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2387796AbfIWU0u (ORCPT ); Mon, 23 Sep 2019 16:26:50 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 23 Sep 2019 13:26:55 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 23 Sep 2019 13:26:49 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 23 Sep 2019 13:26:49 -0700 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Sep 2019 20:26:49 +0000 Received: from [10.110.48.28] (10.124.1.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 23 Sep 2019 20:26:48 +0000 Subject: Re: [PATCH v2 11/11] powerpc/mm/book3s64/pgtable: Uses counting method to skip serializing To: Leonardo Bras , , , Linux-MM CC: Dan Williams , Arnd Bergmann , Jason Gunthorpe , Greg Kroah-Hartman , Mahesh Salgaonkar , YueHaibing , Nicholas Piggin , "Mike Rapoport" , Keith Busch , "Richard Fontana" , Paul Mackerras , "Aneesh Kumar K.V" , Ganesh Goudar , Thomas Gleixner , Ira Weiny , Andrew Morton , "Allison Randal" References: <20190920195047.7703-1-leonardo@linux.ibm.com> <20190920195047.7703-12-leonardo@linux.ibm.com> <1b39eaa7-751d-40bc-d3d7-41aaa15be42a@nvidia.com> <24863d8904c6e05e5dd48cab57db4274675ae654.camel@linux.ibm.com> <4ea26ffb-ad03-bdff-7893-95332b22a5fd@nvidia.com> <18c5c378db98f223a0663034baa9fd6ce42f1ec7.camel@linux.ibm.com> <8706a1f1-0c5e-d152-938b-f355b9a5aaa8@nvidia.com> <1568b3ef-cec9-bf47-edaa-c775c2f544fb@nvidia.com> X-Nvconfidentiality: public From: John Hubbard Message-ID: Date: Mon, 23 Sep 2019 13:26:48 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To DRHQMAIL107.nvidia.com (10.27.9.16) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1569270415; bh=UcV4RD8PsGQCI3ECb3gttt6xlL6KcQV1be+lYQ3oGQI=; h=X-PGP-Universal:Subject:To:CC:References:X-Nvconfidentiality:From: Message-ID:Date:User-Agent:MIME-Version:In-Reply-To: X-Originating-IP:X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=YAC7bHogRtgPIDCGrAn3YjCzVWsG5mEgDTDxy0IU3+mLwhkIoPNwCzaPmkkGtXzRh weRUFOOJlmEy9Sz/dY9f8f5cKPG1i70XQiy0zvGnTY5jMbye/VHXDpEJR1T4o9OGfB o5WA9AES+CeS38or7OUyrSaC45pGe6tGv65N4z6JbSKira2HQY3Jd2VySTKp5W9J/A CALJkz1Yl/xD5KTzh+NhlrunFa876dbixft662iNenv3iHTZjqNQKPesiqAn+5QdIw VlJgjCTT0PkI3TlMJExnI6O/TNKmCor4h/aJX5/1Aec/7io6PzXmjPa3eI64+ugo81 M/LHDE08SxMkA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/23/19 1:23 PM, Leonardo Bras wrote: > On Mon, 2019-09-23 at 12:58 -0700, John Hubbard wrote: >> >> CPU 0 CPU 1 >> ------ -------------- >> READ(pte) (re-ordered at run time) >> atomic_inc(val) (no run-time memory barrier!) >> >> pmd_clear(pte) >> if (val) >> run_on_all_cpus(): IPI >> local_irq_disable() (also not a mem barrier) >> >> if(pte) >> walk page tables > > Let me see if I can understand, > On most patches, it would be: > > CPU 0 CPU 1 > ------ -------------- > ptep = __find_linux_pte > (re-ordered at run time) > atomic_inc(val) > pmd_clear(pte) > smp_mb() > if (val) > run_on_all_cpus(): IPI > local_irq_disable() > > if(ptep) > pte = *ptep; > > Is that what you meant? > > Yes. thanks, -- John Hubbard NVIDIA