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Tue, 24 Sep 2019 08:00:39 +0000 From: "Lowry Li (Arm Technology China)" To: Liviu Dudau , "james qian wang (Arm Technology China)" , "maarten.lankhorst@linux.intel.com" , "seanpaul@chromium.org" , "airlied@linux.ie" , Brian Starkey , Mihail Atanassov CC: "Julien Yin (Arm Technology China)" , "Jonathan Chai (Arm Technology China)" , Ayan Halder , "dri-devel@lists.freedesktop.org" , "linux-kernel@vger.kernel.org" , nd Subject: [PATCH v2 0/2] drm/komeda: Add layer line size support Thread-Topic: [PATCH v2 0/2] drm/komeda: Add layer line size support Thread-Index: AQHVcq4n2NTPDT8buUeD7qC/mk6snA== Date: Tue, 24 Sep 2019 08:00:39 +0000 Message-ID: <20190924080022.19250-1-lowry.li@arm.com> Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [113.29.88.7] x-clientproxiedby: HK0PR01CA0022.apcprd01.prod.exchangelabs.com (2603:1096:203:92::34) To VI1PR08MB5488.eurprd08.prod.outlook.com (2603:10a6:803:137::22) Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Lowry.Li@arm.com; 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X-MS-Office365-Filtering-Correlation-Id-Prvs: a3603b8b-040d-4bb1-72c1-08d740c549c1 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(5600167)(710020)(711020)(4605104)(1401327)(4618075)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(2017052603328)(7193020);SRVR:AM0PR08MB5266; NoDisclaimer: True X-Forefront-PRVS: 0170DAF08C X-Microsoft-Antispam-Message-Info: McRbMF3mDmASgrDli2qtSIXHpPfVXyt2qR1nQhSjRG6b3sACHZ9b5TodroGwjGUDjS4zkP0bBlTOhEc4M3nnM7NQsijPdSbhty07Jbj8pBafqQ6G3a4KLFvShPfOYryVYGkVnHnyUWSgbXk4Acgk70gQbM7JHD6SsCNDmbxNHM+2GmiF53Z8ORQvIj8bqAbBnWoZyF69GDm3yg734waW4IQtxzQNRB+QPtsNQ4bVmHG72HCYUBakIesCz08lxA0BvmYpk2h2NRYU2Q+C04dip34znyKjIZwKrDtilbWCSlZ74WnjS/JvEwUYnGV2+9vsPO/ZcVpRGK3uNhTyTMjr/J7HQCdQjYVRY/cHtn8dWBcpOW6uKit9jiAjdUc6n4Ld6mTIkhn682YnM+zovmD07JbHcW3s09SkboJZW+/NYD8= X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Sep 2019 08:00:51.3770 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8de527e6-bc33-4439-f23b-08d740c55171 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR08MB5266 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, From D32 every component have a line size register to indicate internal fifo size, instead of using the global line_sz. This serie aims at adding the layer line size support and check accordingly on both D71 and D32 or newer. Changes since v1: Rebases to drm-misc-next branch. Lowry Li (Arm Technology China) (2): drm/komeda: Add line size support drm/komeda: Adds layer horizontal input size limitation check for D71 .../arm/display/komeda/d71/d71_component.c | 106 ++++++++++++++++-- .../gpu/drm/arm/display/komeda/d71/d71_regs.h | 9 +- .../drm/arm/display/komeda/komeda_pipeline.h | 2 + .../display/komeda/komeda_pipeline_state.c | 17 +++ 4 files changed, 119 insertions(+), 15 deletions(-) --=20 2.17.1