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[71.197.186.152]) by smtp.gmail.com with ESMTPSA id r28sm3261936pfg.62.2019.09.24.12.10.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 24 Sep 2019 12:10:05 -0700 (PDT) From: Kevin Hilman To: Christian Hewitt , Rob Herring , Mark Rutland , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Frank Hartung , Christian Hewitt Subject: Re: [PATCH] arm64: dts: meson: Add capacity-dmips-mhz attributes to G12B In-Reply-To: <1568429380-3231-1-git-send-email-christianshewitt@gmail.com> References: <1568429380-3231-1-git-send-email-christianshewitt@gmail.com> Date: Tue, 24 Sep 2019 12:10:05 -0700 Message-ID: <7htv915x4i.fsf@baylibre.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Christian Hewitt writes: > From: Frank Hartung > > From: Frank Hartung nit: duplicate From line. Removed when applying. > Meson G12B SoCs (S922X and A311D) are a big-little design where not all CPUs > are equal; the A53s cores are weaker than the A72s. > > Include capacity-dmips-mhz properties to tell the OS there is a difference > in processing capacity. The dmips values are based on similar submissions for > other A53/A72 SoCs: HiSilicon 3660 [1] and Rockchip RK3399 [2]. > > This change is particularly beneficial for use-cases like retro gaming where > emulators often run on a single core. The OS now chooses an A72 core instead > of an A53 core. > > [1] https://lore.kernel.org/patchwork/patch/862742/ > [2] https://patchwork.kernel.org/patch/10836577/ > > Signed-off-by: Frank Hartung > Signed-off-by: Christian Hewitt Queued for v5.5, Thanks! Kevin