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[209.132.180.67]) by mx.google.com with ESMTP id h23si1066495edh.248.2019.09.26.03.20.57; Thu, 26 Sep 2019 03:21:20 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@broadcom.com header.s=google header.b=OiTXVR4B; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=broadcom.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387575AbfIZEpa (ORCPT + 99 others); Thu, 26 Sep 2019 00:45:30 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:35192 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1733042AbfIZEp3 (ORCPT ); Thu, 26 Sep 2019 00:45:29 -0400 Received: by mail-pf1-f196.google.com with SMTP id 205so1047161pfw.2 for ; Wed, 25 Sep 2019 21:45:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=from:to:cc:subject:date:message-id; bh=AgVSoBdBuwz8ttD0kFQ6CIjiHAq68ghhdDV9wOUejaY=; b=OiTXVR4B1o2pOs7KqlBHQYX7ornZRtLbYUU8YEpMGbwPXi4XhdKTDMxZyEJNqYs7oy xGe3UlLXMsic0T3CWpRKgQxz016mcUB8C1/J8sRgV5Oth5AT9KKo30/G2tahoWKEcFg0 3ju5icuFYDhEOwyqW9Uth1X6B0p03RkOy2Q0E= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=AgVSoBdBuwz8ttD0kFQ6CIjiHAq68ghhdDV9wOUejaY=; b=hTZzJJlOFuMlduTaklZnfNA7m4JQ6Gptb5P4njTYqEDB8i1Wx6DgYs8hHtcuJ8ociD knRiwl4NE9KOfXGf5c7Xx++y0b9JzmJ0ENoFaHZRFvg8YA/8OKg+eDk/BPLsqCtiscwn HyZY6Q45nmsY0OcBALSR9RztNxHtT9u9OeB5bVAkK2yE9n1BKzrb6FOvyBw4pJYKWS1L 028M5Sazg+wFoeaxK1zBWWeHKTceZLPNFBXG9HOr5auSjejsrSbDWwLfVxjPh6GK8pyG mMdr3EP0FaGJJNabQNrRRyztMyyFTBU7WIbnqEvN6b+HEDH/lXOj78WmH0hM66ETrAza N33A== X-Gm-Message-State: APjAAAXT1FkqSXOb2mmpQAOprD0KLlWx28/33PMko7LaviIxFnhC7e+4 wusghFP7rhoWxA2FWJajUWVYaQ== X-Received: by 2002:a63:3f49:: with SMTP id m70mr1433832pga.186.1569473128092; Wed, 25 Sep 2019 21:45:28 -0700 (PDT) Received: from rayagonda.dhcp.broadcom.net ([192.19.234.250]) by smtp.gmail.com with ESMTPSA id z22sm623526pgf.10.2019.09.25.21.45.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 25 Sep 2019 21:45:27 -0700 (PDT) From: Rayagonda Kokatanur To: Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, Wolfram Sang , Michael Cheng , Shreesha Rajashekar , Lori Hikichi , linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Rayagonda Kokatanur , Icarus Chau , Ray Jui , Shivaraj Shetty Subject: [PATCH v2 1/1] i2c: iproc: Add i2c repeated start capability Date: Thu, 26 Sep 2019 10:10:08 +0530 Message-Id: <1569472808-15284-1-git-send-email-rayagonda.kokatanur@broadcom.com> X-Mailer: git-send-email 1.9.1 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Lori Hikichi Enable handling of i2c repeated start. The current code handles a multi msg i2c transfer as separate i2c bus transactions. This change will now handle this case using the i2c repeated start protocol. The number of msgs in a transfer is limited to two, and must be a write followed by a read. Signed-off-by: Lori Hikichi Signed-off-by: Rayagonda Kokatanur Signed-off-by: Icarus Chau Signed-off-by: Ray Jui Signed-off-by: Shivaraj Shetty --- changes from v1: - Address code review comment from Wolfram Sang drivers/i2c/busses/i2c-bcm-iproc.c | 63 ++++++++++++++++++++++++++++++-------- 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/drivers/i2c/busses/i2c-bcm-iproc.c b/drivers/i2c/busses/i2c-bcm-iproc.c index d7fd76b..e478db7 100644 --- a/drivers/i2c/busses/i2c-bcm-iproc.c +++ b/drivers/i2c/busses/i2c-bcm-iproc.c @@ -81,6 +81,7 @@ #define M_CMD_PROTOCOL_MASK 0xf #define M_CMD_PROTOCOL_BLK_WR 0x7 #define M_CMD_PROTOCOL_BLK_RD 0x8 +#define M_CMD_PROTOCOL_PROCESS 0xa #define M_CMD_PEC_SHIFT 8 #define M_CMD_RD_CNT_SHIFT 0 #define M_CMD_RD_CNT_MASK 0xff @@ -675,13 +676,20 @@ static int bcm_iproc_i2c_xfer_wait(struct bcm_iproc_i2c_dev *iproc_i2c, return 0; } -static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, - struct i2c_msg *msg) +/* + * If 'process_call' is true, then this is a multi-msg transfer that requires + * a repeated start between the messages. + * More specifically, it must be a write (reg) followed by a read (data). + * The i2c quirks are set to enforce this rule. + */ +static int bcm_iproc_i2c_xfer_internal(struct bcm_iproc_i2c_dev *iproc_i2c, + struct i2c_msg *msgs, bool process_call) { int i; u8 addr; u32 val, tmp, val_intr_en; unsigned int tx_bytes; + struct i2c_msg *msg = &msgs[0]; /* check if bus is busy */ if (!!(iproc_i2c_rd_reg(iproc_i2c, @@ -707,14 +715,29 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, val = msg->buf[i]; /* mark the last byte */ - if (i == msg->len - 1) - val |= BIT(M_TX_WR_STATUS_SHIFT); + if (!process_call && (i == msg->len - 1)) + val |= 1 << M_TX_WR_STATUS_SHIFT; iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); } iproc_i2c->tx_bytes = tx_bytes; } + /* Process the read message if this is process call */ + if (process_call) { + msg++; + iproc_i2c->msg = msg; /* point to second msg */ + + /* + * The last byte to be sent out should be a slave + * address with read operation + */ + addr = i2c_8bit_addr_from_msg(msg); + /* mark it the last byte out */ + val = addr | (1 << M_TX_WR_STATUS_SHIFT); + iproc_i2c_wr_reg(iproc_i2c, M_TX_OFFSET, val); + } + /* mark as incomplete before starting the transaction */ if (iproc_i2c->irq) reinit_completion(&iproc_i2c->done); @@ -733,7 +756,7 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, * underrun interrupt, which will be triggerred when the TX FIFO is * empty. When that happens we can then pump more data into the FIFO */ - if (!(msg->flags & I2C_M_RD) && + if (!process_call && !(msg->flags & I2C_M_RD) && msg->len > iproc_i2c->tx_bytes) val_intr_en |= BIT(IE_M_TX_UNDERRUN_SHIFT); @@ -743,6 +766,8 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, */ val = BIT(M_CMD_START_BUSY_SHIFT); if (msg->flags & I2C_M_RD) { + u32 protocol; + iproc_i2c->rx_bytes = 0; if (msg->len > M_RX_FIFO_MAX_THLD_VALUE) iproc_i2c->thld_bytes = M_RX_FIFO_THLD_VALUE; @@ -758,7 +783,10 @@ static int bcm_iproc_i2c_xfer_single_msg(struct bcm_iproc_i2c_dev *iproc_i2c, /* enable the RX threshold interrupt */ val_intr_en |= BIT(IE_M_RX_THLD_SHIFT); - val |= (M_CMD_PROTOCOL_BLK_RD << M_CMD_PROTOCOL_SHIFT) | + protocol = process_call ? + M_CMD_PROTOCOL_PROCESS : M_CMD_PROTOCOL_BLK_RD; + + val |= (protocol << M_CMD_PROTOCOL_SHIFT) | (msg->len << M_CMD_RD_CNT_SHIFT); } else { val |= (M_CMD_PROTOCOL_BLK_WR << M_CMD_PROTOCOL_SHIFT); @@ -774,17 +802,24 @@ static int bcm_iproc_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg msgs[], int num) { struct bcm_iproc_i2c_dev *iproc_i2c = i2c_get_adapdata(adapter); - int ret, i; + bool process_call = false; + int ret; - /* go through all messages */ - for (i = 0; i < num; i++) { - ret = bcm_iproc_i2c_xfer_single_msg(iproc_i2c, &msgs[i]); - if (ret) { - dev_dbg(iproc_i2c->device, "xfer failed\n"); - return ret; + if (num == 2) { + /* Repeated start, use process call */ + process_call = true; + if (msgs[1].flags & I2C_M_NOSTART) { + dev_err(iproc_i2c->device, "Invalid repeated start\n"); + return -EOPNOTSUPP; } } + ret = bcm_iproc_i2c_xfer_internal(iproc_i2c, msgs, process_call); + if (ret) { + dev_dbg(iproc_i2c->device, "xfer failed\n"); + return ret; + } + return num; } @@ -806,6 +841,8 @@ static uint32_t bcm_iproc_i2c_functionality(struct i2c_adapter *adap) }; static struct i2c_adapter_quirks bcm_iproc_i2c_quirks = { + .flags = I2C_AQ_COMB_WRITE_THEN_READ, + .max_comb_1st_msg_len = M_TX_RX_FIFO_SIZE, .max_read_len = M_RX_MAX_READ_LEN, }; -- 1.9.1