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McKenney" , Boris Brezillon , Thomas Gleixner , Paul Cercueil , Arnd Bergmann , Marcel Ziswiler , Liang Yang , Anders Roxell , , Subject: [v8 0/2] mtd: rawnand: Add Cadence NAND controller driver Date: Thu, 26 Sep 2019 09:08:41 +0100 Message-ID: <20190926080924.19220-1-piotrs@cadence.com> X-Mailer: git-send-email 2.15.0 MIME-Version: 1.0 Content-Type: text/plain X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:64.207.220.243;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10009020)(4636009)(39860400002)(376002)(136003)(346002)(396003)(199004)(189003)(36092001)(476003)(81156014)(81166006)(1076003)(54906003)(26005)(16586007)(36756003)(36906005)(8676002)(1671002)(48376002)(316002)(305945005)(2906002)(42186006)(8936002)(50226002)(2616005)(478600001)(87636003)(6666004)(356004)(7416002)(5660300002)(86362001)(47776003)(70206006)(109986005)(70586007)(4326008)(50466002)(51416003)(336012)(426003)(126002)(486006)(186003)(266003);DIR:OUT;SFP:1101;SCL:1;SRVR:BYAPR07MB5656;H:wcmailrelayl01.cadence.com;FPR:;SPF:SoftFail;LANG:en;PTR:ErrorRetry;A:1;MX:1; X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 945733ea-bf01-4647-706b-08d742592bf6 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600167)(711020)(4605104)(1401327)(2017052603328);SRVR:BYAPR07MB5656; X-MS-TrafficTypeDiagnostic: BYAPR07MB5656: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; X-Forefront-PRVS: 0172F0EF77 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: 82TwS3vPah76qyNCnfOyogGoNHMwJ5tlPMtTL+mEJ1INVFrnkznIEVWw67QWvCuhM4DYHV6N9wDeZvowd1kIB6yt1gpRJ5ZIXngv/DtdOuoeSJ5HQ93pZbksLfpxh0pFRsygeioZcjZwfC8r5YGk+osYb17Kl1rQabzowjese/BpXBHZxRudoHouTbK1n56Ix/dswYFkCydHrdW+vUDLKBN21EUUDPubgZXmUq64Bh042qXqyiGFeXY9osBvM2M/PZr5Q04w1kqqXLwe1uNYNwy5xgdXzEpUHiCCjf2ixJfvrRnqGEY4fjtb+pbYw8RcI6aiDY5aU9khBfQDUJg8pERBKJeNJnn4xiywvpByneCeoAD2OXJYVAefad+94SC2O5oPXQ8r9zUU3CbjVLBwM2yWOTslawFT5VAq4+bhRnA= X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2019 08:11:45.1846 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 945733ea-bf01-4647-706b-08d742592bf6 X-MS-Exchange-CrossTenant-Id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=d36035c5-6ce6-4662-a3dc-e762e61ae4c9;Ip=[64.207.220.243];Helo=[wcmailrelayl01.cadence.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR07MB5656 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-09-26_03:2019-09-25,2019-09-26 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 malwarescore=0 impostorscore=0 bulkscore=0 spamscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 lowpriorityscore=0 phishscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1908290000 definitions=main-1909260080 To: unlisted-recipients:; (no To-header on input) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Driver for Cadence HPNFC NAND flash controller. HW DMA interface Page write and page read operations are executed in Command DMA mode. Commands are defined by DMA descriptors. In CDMA mode controller own DMA engine is used (Master DMA mode). Other operations defined by nand_op_instr are executed in "Generic" mode. In that mode data can be transferred only in by Slave DMA interface. Slave DMA interface can be connected directly to AXI or to an external DMA engine. HW ECC support Cadence NAND controller supports HW BCH correction. ECC is transparent from SW point of view. It means that ECC codes are calculated and written to flash. In read operation ECC codes are removed from user data and correction is made if necessary. Controller data layout with ECC enabled: ------------------------------------------------------------------------- |Sec 1 | ECC | Sec 2 | ECC ...... | Sec n | OOB (32B) | ECC | unused data | ------------------------------------------------------------------------- Last sector is extended by a out-bound data. Tha maximum size of "extra data" is 32 bytes. The oob data are protected by ECC. If we need to read only oob data the whole last sector must be read. It is because oob data are part of last sector. Reading oob function always reads whole sector and writing oob function always writes whole last sector. Written data are interleaved with the ECC therefore part of the last sector is located on oob area and the BBM is overwritten. SKIP BYTES feature To protect BBM the "skip byte" HW feature is used. Write page function copies BBM value from first byte of oob data to BBM offset defined by manufacturer. Read page functions always takes BBM from flash manufacturer offset. It causes that for not written pages the proper value of BBM marker is used. ECC size calculation Information about supported ECC steps and ECC strengths are read from controller registers. ECC sector size and ECC strength can be configurable. Size of ECC depends on maximum supported sector size it not depends on selected sector size. Therefore there is a separate function for calculating ECC size for each of possible sector size/step size. Piotr Sroka (2): Add new Cadence NAND driver to MTD subsystem Add Cadence NAND controller driver .../bindings/mtd/cadence-nand-controller.txt | 53 + MAINTAINERS | 7 + drivers/mtd/nand/raw/Kconfig | 7 + drivers/mtd/nand/raw/Makefile | 1 + drivers/mtd/nand/raw/cadence-nand-controller.c | 3031 ++++++++++++++++++++ 5 files changed, 3099 insertions(+) create mode 100644 Documentation/devicetree/bindings/mtd/cadence-nand-controller.txt create mode 100644 drivers/mtd/nand/raw/cadence-nand-controller.c -- 2.15.0