Received: by 2002:a25:824b:0:0:0:0:0 with SMTP id d11csp1893270ybn; Thu, 26 Sep 2019 03:55:49 -0700 (PDT) X-Google-Smtp-Source: APXvYqyQ6RZpBHkjrFSKeBUUoUMN1z8aBtd55jO5vxEsSa9FuF0ze3v4wWC4mqlaFVEz2k8s/V58 X-Received: by 2002:a05:6402:1a45:: with SMTP id bf5mr2721281edb.275.1569495349087; Thu, 26 Sep 2019 03:55:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569495349; cv=none; d=google.com; s=arc-20160816; b=kgDD+rZjeySbdCHcXRkZeOlara6KyMGsmzuUadHnUmga2Po6zsTdVe0q/9CkAoXQkv 2F6LgMbHg3CJiu8XpaiY+2KhDZLr1ssLi41sxApIlsS3mV8qdXF8gyHextZzoOfSFlVO IcMCTuBSKdwBOPTGFyuSFyyb/YPZ7jpET+0PAhbizSpO3CJEAxHo7nib+A9r8JYrql2h Psf/g7r5rNOnwJfjZgp4n0jC0cJRmxMdbXgzLyCdwTGX0AYIL1BG7/2DypvRAI0ZUlra 3qEgz1yRMr8NS3gRYFi16bn8yFl8jjIxdzL6CvxzNiqYAgCUOk0nGVabf4Vt+8fd/hv4 LJPg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=K5YHxdaEAQ1X15X2ngO/MpjAxquy/C21di+S+a5zucA=; b=cejbafIijFP0olUcwBLwsSTaQ4xGikqos09glC13xci7/MeVWKSsIdFInPWFTqAt3d ewHlXYNSo3Syp0aUMEySJbVkQ2Jm4trJo42TEKSyRzBmE6irbRuFw/AvK0EJzcWlgh/M BV5OQeU/LSw/v2sro84INY6Kbmpey01csLHqbL/LIv/fTwsa3sTjh/r+SInxyRlNIVzl x+3uHeFBrG1iKU/wSiuKAgjYvISSpO2CG9pdIUuW0RjNjs9jA6znDVZ6Hyaw0os8Q84M 7ygHJGL1XxNocRgMsO/CDKNtJsCAnArXv3t32vj2h4etzFhBphvcAMxu0U6jeFMThzwj jaIA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y11si767559eje.365.2019.09.26.03.55.25; Thu, 26 Sep 2019 03:55:49 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2407997AbfIYOei (ORCPT + 99 others); Wed, 25 Sep 2019 10:34:38 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47216 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730669AbfIYOeh (ORCPT ); Wed, 25 Sep 2019 10:34:37 -0400 X-UUID: 1fed44208310455bbdbc54d2b24f3828-20190925 X-UUID: 1fed44208310455bbdbc54d2b24f3828-20190925 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 300394955; Wed, 25 Sep 2019 22:34:28 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 25 Sep 2019 22:34:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 25 Sep 2019 22:34:27 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v10 07/12] dt-bindings: pwm: pwm-mediatek: add a property "num-pwms" Date: Wed, 25 Sep 2019 22:32:32 +0800 Message-ID: <1569421957-20765-8-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1569421957-20765-1-git-send-email-sam.shih@mediatek.com> References: <1569421957-20765-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" in example so that we could specify the number of PWM channels via device tree. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Matthias Brugger Acked-by: Uwe Kleine-König --- Changes since v10: 1. Follow reviewers's comments: - derive the number of PWMs from the specific compatible string 2. Add mt7629 pwm description 3. Add mt7628 fixed-clock description Changes since v6: Follow reviewers's comments: - The subject should indicate this is for Mediatek Changes since v5: - Add an Acked-by tag - This file is original v4 patch 5/10 (https://patchwork.kernel.org/patch/11102577/) --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 991728cb46cb..975d7871830d 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -9,17 +9,20 @@ Required properties: - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of the cell format. - - clocks: phandle and clock specifier of the PWM reference clock. - - clock-names: must contain the following, except for MT7628 which - has no clocks + - clocks: One phandle and clock specifier for each entry in the "clock-names" + property, Use fixed-clock as dummy clocks for mt7628 + - clock-names: must contain the following - "top": the top clock generator - "main": clock used by the PWM core - "pwm1-8": the eight per PWM clocks for mt2712 - "pwm1-6": the six per PWM clocks for mt7622 - "pwm1-5": the five per PWM clocks for mt7623 + - "pwm1-4": the four per PWM clocks for mt7628 + - "pwm1": the PWM1 clock for mt7629 - pinctrl-names: Must contain a "default" entry. - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. + - num-pwms: the number of PWM channels. Example: pwm0: pwm@11006000 { @@ -37,4 +40,5 @@ Example: "pwm3", "pwm4", "pwm5"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins>; + num-pwms = <5>; }; -- 2.17.1