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[209.132.180.67]) by mx.google.com with ESMTP id g18si833685edq.209.2019.09.26.22.17.20; Thu, 26 Sep 2019 22:17:44 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726033AbfI0FOy (ORCPT + 99 others); Fri, 27 Sep 2019 01:14:54 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:38455 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725268AbfI0FOy (ORCPT ); Fri, 27 Sep 2019 01:14:54 -0400 X-UUID: 45376460567e4833912fd5f52c874093-20190927 X-UUID: 45376460567e4833912fd5f52c874093-20190927 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1544338163; Fri, 27 Sep 2019 13:14:50 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 27 Sep 2019 13:14:46 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 27 Sep 2019 13:14:46 +0800 Message-ID: <1569561287.2428.6.camel@mtkswgap22> Subject: Re: [PATCH v6 1/5] pinctrl: mediatek: Check gpio pin number and use binary search in mtk_hw_pin_field_lookup() From: Light Hsieh To: CC: , , , , Date: Fri, 27 Sep 2019 13:14:47 +0800 In-Reply-To: <1569560532-1886-1-git-send-email-light.hsieh@mediatek.com> References: <1569560532-1886-1-git-send-email-light.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-TM-SNTS-SMTP: C11C61617888C742E4237027CA9173895FD50B1C77B35BACF510E8BDAAA5B69F2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear reviewers: Patch v6 improves v5 by: 1.in mtk_pinconf_get() and mtk_pinconf_set() @pinctrl-paris.c: * check if pin is in range before using pin as array index of hw->soc->pins[] 2.in mtk_pin_field_lookup() @pinctrl-mtk-common-v2.c: * declear start, end, check as signed integer instead of unsigned integer. Otherwise, kernel fault will occur when s_pin field of first entry of a mtk_pin_field_calc[] array is not 0. On Fri, 2019-09-27 at 13:02 +0800, Light Hsieh wrote: > 1. Check if gpio pin number is in valid range to prevent from get invalid > pointer 'desc' in the following code: > desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; > > 2. Use binary search in mtk_hw_pin_field_lookup() > Modify mtk_hw_pin_field_lookup() to use binary search for accelerating > search. > > --- > drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 25 +++++++++++++++++++----- > drivers/pinctrl/mediatek/pinctrl-paris.c | 25 ++++++++++++++++++++++++ > 2 files changed, 45 insertions(+), 5 deletions(-) > > diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > index 20e1c89..8077855 100644 > --- a/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > +++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c > @@ -68,7 +68,8 @@ static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, > { > const struct mtk_pin_field_calc *c, *e; > const struct mtk_pin_reg_calc *rc; > - u32 bits; > + u32 bits, found = 0; > + int start = 0, end, check; > > if (hw->soc->reg_cal && hw->soc->reg_cal[field].range) { > rc = &hw->soc->reg_cal[field]; > @@ -79,21 +80,32 @@ static int mtk_hw_pin_field_lookup(struct mtk_pinctrl *hw, > return -ENOTSUPP; > } > > + end = rc->nranges - 1; > c = rc->range; > e = c + rc->nranges; > > - while (c < e) { > - if (desc->number >= c->s_pin && desc->number <= c->e_pin) > + while (start <= end) { > + check = (start + end) >> 1; > + if (desc->number >= rc->range[check].s_pin > + && desc->number <= rc->range[check].e_pin) { > + found = 1; > break; > - c++; > + } else if (start == end) > + break; > + else if (desc->number < rc->range[check].s_pin) > + end = check - 1; > + else > + start = check + 1; > } > > - if (c >= e) { > + if (!found) { > dev_dbg(hw->dev, "Not support field %d for pin = %d (%s)\n", > field, desc->number, desc->name); > return -ENOTSUPP; > } > > + c = rc->range + check; > + > if (c->i_base > hw->nbase - 1) { > dev_err(hw->dev, > "Invalid base for field %d for pin = %d (%s)\n", > @@ -182,6 +194,9 @@ int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, > if (err) > return err; > > + if (value < 0 || value > pf.mask) > + return -EINVAL; > + > if (!pf.next) > mtk_rmw(hw, pf.index, pf.offset, pf.mask << pf.bitpos, > (value & pf.mask) << pf.bitpos); > diff --git a/drivers/pinctrl/mediatek/pinctrl-paris.c b/drivers/pinctrl/mediatek/pinctrl-paris.c > index 923264d..3e13ae7 100644 > --- a/drivers/pinctrl/mediatek/pinctrl-paris.c > +++ b/drivers/pinctrl/mediatek/pinctrl-paris.c > @@ -81,6 +81,8 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, > int val, val2, err, reg, ret = 1; > const struct mtk_pin_desc *desc; > > + if (pin >= hw->soc->npins) > + return -EINVAL; > desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; > > switch (param) { > @@ -206,6 +208,10 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, > int err = 0; > u32 reg; > > + if (pin >= hw->soc->npins) { > + err = -EINVAL; > + goto err; > + } > desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; > > switch ((u32)param) { > @@ -693,6 +699,9 @@ static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio) > const struct mtk_pin_desc *desc; > int value, err; > > + if (gpio > hw->soc->npins) > + return -EINVAL; > + > desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; > > err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value); > @@ -708,6 +717,9 @@ static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio) > const struct mtk_pin_desc *desc; > int value, err; > > + if (gpio > hw->soc->npins) > + return -EINVAL; > + > desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; > > err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value); > @@ -722,6 +734,9 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) > struct mtk_pinctrl *hw = gpiochip_get_data(chip); > const struct mtk_pin_desc *desc; > > + if (gpio > hw->soc->npins) > + return; > + > desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio]; > > mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value); > @@ -729,12 +744,22 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value) > > static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio) > { > + struct mtk_pinctrl *hw = gpiochip_get_data(chip); > + > + if (gpio > hw->soc->npins) > + return -EINVAL; > + > return pinctrl_gpio_direction_input(chip->base + gpio); > } > > static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio, > int value) > { > + struct mtk_pinctrl *hw = gpiochip_get_data(chip); > + > + if (gpio > hw->soc->npins) > + return -EINVAL; > + > mtk_gpio_set(chip, gpio, value); > > return pinctrl_gpio_direction_output(chip->base + gpio);