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Sun, 29 Sep 2019 03:26:38 +0000 From: "james qian wang (Arm Technology China)" To: Sandy Huang CC: "dri-devel@lists.freedesktop.org" , Maarten Lankhorst , Maxime Ripard , Sean Paul , David Airlie , Daniel Vetter , "linux-kernel@vger.kernel.org" , nd Subject: Re: [v2,1/3] drm: Add some new format DRM_FORMAT_NVXX_10 Thread-Topic: [v2,1/3] drm: Add some new format DRM_FORMAT_NVXX_10 Thread-Index: AQHVdnWzqsA4YhPoH0G4L3W1+ovDcg== Date: Sun, 29 Sep 2019 03:26:38 +0000 Message-ID: <20190929032630.GA26869@jamwan02-TSP300> References: <1569486289-152061-2-git-send-email-hjc@rock-chips.com> In-Reply-To: <1569486289-152061-2-git-send-email-hjc@rock-chips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mutt/1.10.1 (2018-07-13) x-originating-ip: [113.29.88.7] x-clientproxiedby: HK2PR0401CA0008.apcprd04.prod.outlook.com (2603:1096:202:2::18) To VE1PR08MB5006.eurprd08.prod.outlook.com (2603:10a6:803:113::31) Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=james.qian.wang@arm.com; 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X-MS-Office365-Filtering-Correlation-Id-Prvs: 1855e459-4ddd-41f2-5502-08d7448cd665 NoDisclaimer: True X-Forefront-PRVS: 017589626D X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: GHFARzGd64kh/0KzhcPPavdmhlMFbiUTmlAJPt6HQFvWhYm9tXQTP85eujqNMrXiOogApusq+o9GOCHOINQfWDsKxlRGyKZVweaLsdgUVXVvIX0VMG+XnfVO9Jny4ZMQfNgz9JzpJ+TpIurTFoW9oc8YD//HJdn63XW+MByvKD6tM7eYTd8WZ/z0KawxkEZdE0Hf1ktszlqNLOS9YQNSg6/88vaJ2qcUR0e6d7E7ofmnQeiBYnh04MaxR/uBjoSf2sjot62jYnQyKEpfoca6qcPGu3D97tJ01LO+3CGfM5/YjLovBn0SrjIIXOPYFPco0zE304a4NcJQI4E0ftMtK24B53FKvvvQvftrCp/Ddv9ae6IsXhjFvvVvj5cCf+sHoHPzVV1WeD2Nd1y8LfyHG0n0jXapQQwBV3heDi5DMGE= X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Sep 2019 03:26:47.7797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fc2abbb1-47d0-4d2a-ed70-08d7448cdc4b X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR08MB4678 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 26, 2019 at 04:24:47PM +0800, Sandy Huang wrote: > These new format is supported by some rockchip socs: >=20 > DRM_FORMAT_NV12_10/DRM_FORMAT_NV21_10 > DRM_FORMAT_NV16_10/DRM_FORMAT_NV61_10 > DRM_FORMAT_NV24_10/DRM_FORMAT_NV42_10 >=20 > Signed-off-by: Sandy Huang > --- > drivers/gpu/drm/drm_fourcc.c | 18 ++++++++++++++++++ > include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++ > 2 files changed, 32 insertions(+) >=20 > diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c > index c630064..ccd78a3 100644 > --- a/drivers/gpu/drm/drm_fourcc.c > +++ b/drivers/gpu/drm/drm_fourcc.c > @@ -261,6 +261,24 @@ const struct drm_format_info *__drm_format_info(u32 = format) > { .format =3D DRM_FORMAT_P016, .depth =3D 0, .num_planes =3D 2, > .char_per_block =3D { 2, 4, 0 }, .block_w =3D { 1, 0, 0 }, .block_h = =3D { 1, 0, 0 }, > .hsub =3D 2, .vsub =3D 2, .is_yuv =3D true}, > + { .format =3D DRM_FORMAT_NV12_10, .depth =3D 0, .num_planes =3D 2, > + .char_per_block =3D { 5, 10, 0 }, .block_w =3D { 4, 4, 0 }, .block_h= =3D { 4, 4, 0 }, Hi Sandy: Their is a problem here for char_per_block size of plane[0]: Since: 5 * 8 !=3D 4 * 4 * 10; Seems you mis-set the block_w/h, per your block size the block is 2x2, and = it should be: .char_per_block =3D { 5, 10, 0 }, .block_w =3D { 2, 2, 0 }, .block_h =3D {= 2, 2, 0 }, Best Regards: James > + .hsub =3D 2, .vsub =3D 2, .is_yuv =3D true}, > + { .format =3D DRM_FORMAT_NV21_10, .depth =3D 0, .num_planes =3D 2, > + .char_per_block =3D { 5, 10, 0 }, .block_w =3D { 4, 4, 0 }, .block_h= =3D { 4, 4, 0 }, > + .hsub =3D 2, .vsub =3D 2, .is_yuv =3D true}, > + { .format =3D DRM_FORMAT_NV16_10, .depth =3D 0, .num_planes =3D 2, > + .char_per_block =3D { 5, 10, 0 }, .block_w =3D { 4, 4, 0 }, .block_h= =3D { 4, 4, 0 }, > + .hsub =3D 2, .vsub =3D 1, .is_yuv =3D true}, > + { .format =3D DRM_FORMAT_NV61_10, .depth =3D 0, .num_planes =3D 2, > + .char_per_block =3D { 5, 10, 0 }, .block_w =3D { 4, 4, 0 }, .block_h= =3D { 4, 4, 0 }, > + .hsub =3D 2, .vsub =3D 1, .is_yuv =3D true}, > + { .format =3D DRM_FORMAT_NV24_10, .depth =3D 0, .num_planes =3D 2, > + .char_per_block =3D { 5, 10, 0 }, .block_w =3D { 4, 4, 0 }, .block_h= =3D { 4, 4, 0 }, > + .hsub =3D 1, .vsub =3D 1, .is_yuv =3D true}, > + { .format =3D DRM_FORMAT_NV42_10, .depth =3D 0, .num_planes =3D 2, > + .char_per_block =3D { 5, 10, 0 }, .block_w =3D { 4, 4, 0 }, .block_h= =3D { 4, 4, 0 }, > + .hsub =3D 1, .vsub =3D 1, .is_yuv =3D true}, > { .format =3D DRM_FORMAT_P210, .depth =3D 0, > .num_planes =3D 2, .char_per_block =3D { 2, 4, 0 }, > .block_w =3D { 1, 0, 0 }, .block_h =3D { 1, 0, 0 }, .hsub =3D 2, > diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.= h > index 3feeaa3..08e2221 100644 > --- a/include/uapi/drm/drm_fourcc.h > +++ b/include/uapi/drm/drm_fourcc.h > @@ -238,6 +238,20 @@ extern "C" { > #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampl= ed Cb:Cr plane */ > =20 > /* > + * 2 plane YCbCr > + * index 0 =3D Y plane, Y3:Y2:Y1:Y0 10:10:10:10 > + * index 1 =3D Cb:Cr plane, Cb3:Cr3:Cb2:Cr2:Cb1:Cr1:Cb0:Cr0 10:10:10:10:= 10:10:10:10 > + * or > + * index 1 =3D Cr:Cb plane, Cr3:Cb3:Cr2:Cb2:Cr1:Cb1:Cr0:Cb0 10:10:10:10:= 10:10:10:10 > + */ > +#define DRM_FORMAT_NV12_10 fourcc_code('N', 'A', '1', '2') /* 2x2 subsam= pled Cr:Cb plane */ > +#define DRM_FORMAT_NV21_10 fourcc_code('N', 'A', '2', '1') /* 2x2 subsam= pled Cb:Cr plane */ > +#define DRM_FORMAT_NV16_10 fourcc_code('N', 'A', '1', '6') /* 2x1 subsam= pled Cr:Cb plane */ > +#define DRM_FORMAT_NV61_10 fourcc_code('N', 'A', '6', '1') /* 2x1 subsam= pled Cb:Cr plane */ > +#define DRM_FORMAT_NV24_10 fourcc_code('N', 'A', '2', '4') /* non-subsam= pled Cr:Cb plane */ > +#define DRM_FORMAT_NV42_10 fourcc_code('N', 'A', '4', '2') /* non-subsam= pled Cb:Cr plane */ > + > +/* > * 2 plane YCbCr MSB aligned > * index 0 =3D Y plane, [15:0] Y:x [10:6] little endian > * index 1 =3D Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian