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From:   Brian Starkey <Brian.Starkey@arm.com>
To:     Ayan Halder <Ayan.Halder@arm.com>
CC:     Liviu Dudau <Liviu.Dudau@arm.com>,
        "malidp@foss.arm.com" <malidp@foss.arm.com>,
        "airlied@linux.ie" <airlied@linux.ie>,
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        <maarten.lankhorst@linux.intel.com>,
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        "daniel@ffwll.ch" <daniel@ffwll.ch>,
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        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "yuq825@gmail.com" <yuq825@gmail.com>, nd <nd@arm.com>,
        Raymond Smith <Raymond.Smith@arm.com>
Subject: Re: [PATCH v2] drm/fourcc: Add Arm 16x16 block modifier
Thread-Topic: [PATCH v2] drm/fourcc: Add Arm 16x16 block modifier
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Date:   Mon, 30 Sep 2019 17:02:37 +0000
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Hi Ayan,

Could we preserve Ray's authorship on this patch?

On Mon, Sep 30, 2019 at 04:44:38PM +0000, Ayan Halder wrote:
> Add the DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED modifier to
> denote the 16x16 block u-interleaved format used in Arm Utgard and
> Midgard GPUs.
>=20
> Changes from v1:-
> 1. Reserved the upper four bits (out of the 56 bits assigned to each vend=
or)
> to denote the category of Arm specific modifiers. Currently, we have two
> categories ie AFBC and MISC.
>=20
> Signed-off-by: Raymond Smith <raymond.smith@arm.com>
> Signed-off-by: Ayan kumar halder <ayan.halder@arm.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 27 ++++++++++++++++++++++++++-
>  1 file changed, 26 insertions(+), 1 deletion(-)
>=20
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.=
h
> index 3feeaa3f987a..b1d3de961109 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -648,7 +648,21 @@ extern "C" {
>   * Further information on the use of AFBC modifiers can be found in
>   * Documentation/gpu/afbc.rst
>   */
> -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode)	fourcc_mod_code(ARM, __afbc=
_mode)
> +
> +/*
> + * The top 4 bits (out of the 56 bits alloted for specifying vendor spec=
ific
> + * modifiers) denote the category for modifiers. Currently we have only =
two
> + * categories of modifiers ie AFBC and MISC. We can have a maximum of si=
xteen
> + * different categories.
> + */

Yeah, this makes more sense than getting crazy with saving bits. Sorry
Qiang/Daniel for not just going with this in the first instance when
you both suggested it.

> +#define DRM_FORMAT_MOD_ARM_CODE(type, val) \
> +	fourcc_mod_code(ARM, ((__u64)type << 52) | ((val) & 0x000fffffffffffffU=
LL))

Not a big deal, but I might prefix type and val with "__" to reduce
the chance of name collisions with code using the macro:
DRM_FORMAT_MOD_ARM_CODE(__type, __val).

> +
> +#define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
> +#define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
> +
> +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
> +	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
> =20
>  /*
>   * AFBC superblock size
> @@ -742,6 +756,17 @@ extern "C" {
>   */
>  #define AFBC_FORMAT_MOD_BCH     (1ULL << 11)
> =20
> +/*
> + * Arm 16x16 Block U-Interleaved modifier
> + *
> + * This is used by Arm Mali Utgard and Midgard GPUs. It divides the imag=
e
> + * into 16x16 pixel blocks. Blocks are stored linearly in order, but pix=
els
> + * in the block are reordered.
> + */
> +#define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
> +	DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
> +
> +

I think you can drop this newline, there's no extra space between any
of the other definitions.

With this line dropped, and if you fix up the author:

Reviewed-by: Brian Starkey <brian.starkey@arm.com>

Thanks for the respin,
-Brian

>  /*
>   * Allwinner tiled modifier
>   *
> --=20
> 2.23.0
>=20