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Mon, 30 Sep 2019 23:08:15 +0000 From: Paul Burton To: "linux-mips@vger.kernel.org" CC: Huacai Chen , Jiaxun Yang , "linux-kernel@vger.kernel.org" , Paul Burton Subject: [PATCH 01/37] MIPS: Unify sc beqz definition Thread-Topic: [PATCH 01/37] MIPS: Unify sc beqz definition Thread-Index: AQHVd+Pwc/PZwTOkWk+5nsJHrv9cbQ== Date: Mon, 30 Sep 2019 23:08:15 +0000 Message-ID: <20190930230806.2940505-2-paul.burton@mips.com> References: <20190930230806.2940505-1-paul.burton@mips.com> In-Reply-To: <20190930230806.2940505-1-paul.burton@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR21CA0006.namprd21.prod.outlook.com (2603:10b6:a03:114::16) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:18::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.23.0 x-originating-ip: [12.94.197.246] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0e672a2c-5249-42c0-2cfe-08d745fb12b8 x-ms-traffictypediagnostic: MWHPR2201MB1709: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4502; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0e672a2c-5249-42c0-2cfe-08d745fb12b8 X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2019 23:08:15.1661 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: a2vXDTOHSXPvOWdjRUlkP0jpNnHxVeSwWleMAjarmzfT/WsrQqd57nGZaHHQMT85vA9yn9Eujku0l9D8Lo2Ogw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1709 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org We currently duplicate the definition of __scbeqz in asm/atomic.h & asm/cmpxchg.h. Move it to asm/llsc.h & rename it to __SC_BEQZ to fit better with the existing __SC macro provided there. We include a tab in the string in order to avoid the need for users to indent code any further to include whitespace of their own after the instruction mnemonic. Signed-off-by: Paul Burton --- arch/mips/include/asm/atomic.h | 28 +++++++++------------------- arch/mips/include/asm/cmpxchg.h | 20 ++++---------------- arch/mips/include/asm/llsc.h | 11 +++++++++++ 3 files changed, 24 insertions(+), 35 deletions(-) diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.= h index bb8658cc7f12..7578c807ef98 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -20,19 +20,9 @@ #include #include #include +#include #include =20 -/* - * Using a branch-likely instruction to check the result of an sc instruct= ion - * works around a bug present in R10000 CPUs prior to revision 3.0 that co= uld - * cause ll-sc sequences to execute non-atomically. - */ -#if R10000_LLSC_WAR -# define __scbeqz "beqzl" -#else -# define __scbeqz "beqz" -#endif - #define ATOMIC_INIT(i) { (i) } =20 /* @@ -65,7 +55,7 @@ static __inline__ void atomic_##op(int i, atomic_t * v) = \ "1: ll %0, %1 # atomic_" #op " \n" \ " " #asm_op " %0, %2 \n" \ " sc %0, %1 \n" \ - "\t" __scbeqz " %0, 1b \n" \ + "\t" __SC_BEQZ "%0, 1b \n" \ " .set pop \n" \ : "=3D&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \ : "Ir" (i) : __LLSC_CLOBBER); \ @@ -93,7 +83,7 @@ static __inline__ int atomic_##op##_return_relaxed(int i,= atomic_t * v) \ "1: ll %1, %2 # atomic_" #op "_return \n" \ " " #asm_op " %0, %1, %3 \n" \ " sc %0, %2 \n" \ - "\t" __scbeqz " %0, 1b \n" \ + "\t" __SC_BEQZ "%0, 1b \n" \ " " #asm_op " %0, %1, %3 \n" \ " .set pop \n" \ : "=3D&r" (result), "=3D&r" (temp), \ @@ -127,7 +117,7 @@ static __inline__ int atomic_fetch_##op##_relaxed(int i= , atomic_t * v) \ "1: ll %1, %2 # atomic_fetch_" #op " \n" \ " " #asm_op " %0, %1, %3 \n" \ " sc %0, %2 \n" \ - "\t" __scbeqz " %0, 1b \n" \ + "\t" __SC_BEQZ "%0, 1b \n" \ " .set pop \n" \ " move %0, %1 \n" \ : "=3D&r" (result), "=3D&r" (temp), \ @@ -205,7 +195,7 @@ static __inline__ int atomic_sub_if_positive(int i, ato= mic_t * v) " .set push \n" " .set "MIPS_ISA_LEVEL" \n" " sc %1, %2 \n" - "\t" __scbeqz " %1, 1b \n" + "\t" __SC_BEQZ "%1, 1b \n" "2: \n" " .set pop \n" : "=3D&r" (result), "=3D&r" (temp), @@ -267,7 +257,7 @@ static __inline__ void atomic64_##op(s64 i, atomic64_t = * v) \ "1: lld %0, %1 # atomic64_" #op " \n" \ " " #asm_op " %0, %2 \n" \ " scd %0, %1 \n" \ - "\t" __scbeqz " %0, 1b \n" \ + "\t" __SC_BEQZ "%0, 1b \n" \ " .set pop \n" \ : "=3D&r" (temp), "+" GCC_OFF_SMALL_ASM() (v->counter) \ : "Ir" (i) : __LLSC_CLOBBER); \ @@ -295,7 +285,7 @@ static __inline__ s64 atomic64_##op##_return_relaxed(s6= 4 i, atomic64_t * v) \ "1: lld %1, %2 # atomic64_" #op "_return\n" \ " " #asm_op " %0, %1, %3 \n" \ " scd %0, %2 \n" \ - "\t" __scbeqz " %0, 1b \n" \ + "\t" __SC_BEQZ "%0, 1b \n" \ " " #asm_op " %0, %1, %3 \n" \ " .set pop \n" \ : "=3D&r" (result), "=3D&r" (temp), \ @@ -329,7 +319,7 @@ static __inline__ s64 atomic64_fetch_##op##_relaxed(s64= i, atomic64_t * v) \ "1: lld %1, %2 # atomic64_fetch_" #op "\n" \ " " #asm_op " %0, %1, %3 \n" \ " scd %0, %2 \n" \ - "\t" __scbeqz " %0, 1b \n" \ + "\t" __SC_BEQZ "%0, 1b \n" \ " move %0, %1 \n" \ " .set pop \n" \ : "=3D&r" (result), "=3D&r" (temp), \ @@ -404,7 +394,7 @@ static __inline__ s64 atomic64_sub_if_positive(s64 i, a= tomic64_t * v) " move %1, %0 \n" " bltz %0, 1f \n" " scd %1, %2 \n" - "\t" __scbeqz " %1, 1b \n" + "\t" __SC_BEQZ "%1, 1b \n" "1: \n" " .set pop \n" : "=3D&r" (result), "=3D&r" (temp), diff --git a/arch/mips/include/asm/cmpxchg.h b/arch/mips/include/asm/cmpxch= g.h index 79bf34efbc04..5d3f0e3513b4 100644 --- a/arch/mips/include/asm/cmpxchg.h +++ b/arch/mips/include/asm/cmpxchg.h @@ -11,19 +11,9 @@ #include #include #include +#include #include =20 -/* - * Using a branch-likely instruction to check the result of an sc instruct= ion - * works around a bug present in R10000 CPUs prior to revision 3.0 that co= uld - * cause ll-sc sequences to execute non-atomically. - */ -#if R10000_LLSC_WAR -# define __scbeqz "beqzl" -#else -# define __scbeqz "beqz" -#endif - /* * These functions doesn't exist, so if they are called you'll either: * @@ -57,7 +47,7 @@ extern unsigned long __xchg_called_with_bad_pointer(void) " move $1, %z3 \n" \ " .set " MIPS_ISA_ARCH_LEVEL " \n" \ " " st " $1, %1 \n" \ - "\t" __scbeqz " $1, 1b \n" \ + "\t" __SC_BEQZ "$1, 1b \n" \ " .set pop \n" \ : "=3D&r" (__ret), "=3D" GCC_OFF_SMALL_ASM() (*m) \ : GCC_OFF_SMALL_ASM() (*m), "Jr" (val) \ @@ -130,7 +120,7 @@ static inline unsigned long __xchg(volatile void *ptr, = unsigned long x, " move $1, %z4 \n" \ " .set "MIPS_ISA_ARCH_LEVEL" \n" \ " " st " $1, %1 \n" \ - "\t" __scbeqz " $1, 1b \n" \ + "\t" __SC_BEQZ "$1, 1b \n" \ " .set pop \n" \ "2: \n" \ : "=3D&r" (__ret), "=3D" GCC_OFF_SMALL_ASM() (*m) \ @@ -268,7 +258,7 @@ static inline unsigned long __cmpxchg64(volatile void *= ptr, /* Attempt to store new at ptr */ " scd %L1, %2 \n" /* If we failed, loop! */ - "\t" __scbeqz " %L1, 1b \n" + "\t" __SC_BEQZ "%L1, 1b \n" " .set pop \n" "2: \n" : "=3D&r"(ret), @@ -311,6 +301,4 @@ static inline unsigned long __cmpxchg64(volatile void *= ptr, # endif /* !CONFIG_SMP */ #endif /* !CONFIG_64BIT */ =20 -#undef __scbeqz - #endif /* __ASM_CMPXCHG_H */ diff --git a/arch/mips/include/asm/llsc.h b/arch/mips/include/asm/llsc.h index c6d17d171147..9b19f38562ac 100644 --- a/arch/mips/include/asm/llsc.h +++ b/arch/mips/include/asm/llsc.h @@ -25,4 +25,15 @@ #define __EXT "dext " #endif =20 +/* + * Using a branch-likely instruction to check the result of an sc instruct= ion + * works around a bug present in R10000 CPUs prior to revision 3.0 that co= uld + * cause ll-sc sequences to execute non-atomically. + */ +#if R10000_LLSC_WAR +# define __SC_BEQZ "beqzl " +#else +# define __SC_BEQZ "beqz " +#endif + #endif /* __ASM_LLSC_H */ --=20 2.23.0