Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Paul Burton <paul.burton@mips.com>
To:     "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
CC:     Huacai Chen <chenhc@lemote.com>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Paul Burton <pburton@wavecomp.com>
Subject: [PATCH 02/37] MIPS: Use compact branch for LL/SC loops on MIPSr6+
Thread-Topic: [PATCH 02/37] MIPS: Use compact branch for LL/SC loops on
 MIPSr6+
Thread-Index: AQHVd+PwLwYhLPuiu0W9q5wn/sVxdw==
Date:   Mon, 30 Sep 2019 23:08:16 +0000
Message-ID: <20190930230806.2940505-3-paul.burton@mips.com>
References: <20190930230806.2940505-1-paul.burton@mips.com>
In-Reply-To: <20190930230806.2940505-1-paul.burton@mips.com>
Accept-Language: en-US
Content-Language: en-US
x-ms-exchange-messagesentrepresentingtype: 1
x-mailer: git-send-email 2.23.0
x-originating-ip: [12.94.197.246]
x-ms-publictraffictype: Email
x-ms-office365-filtering-correlation-id: b1826e22-3325-4626-d08f-08d745fb1342
x-ms-traffictypediagnostic: MWHPR2201MB1709:
x-ms-exchange-transport-forked: True
x-microsoft-antispam-prvs: <MWHPR2201MB1709C6554E2470A028EC46F6C1820@MWHPR2201MB1709.namprd22.prod.outlook.com>
x-ms-oob-tlc-oobclassifiers: OLM:4125;
x-forefront-prvs: 01762B0D64
x-forefront-antispam-report: SFV:NSPM;SFS:(10019020)(366004)(39840400004)(376002)(346002)(396003)(136003)(199004)(189003)(2351001)(66476007)(66556008)(66946007)(64756008)(66446008)(107886003)(99286004)(6486002)(52116002)(5640700003)(6436002)(25786009)(478600001)(14454004)(76176011)(26005)(6512007)(5660300002)(71200400001)(71190400001)(4744005)(1076003)(4326008)(186003)(42882007)(6506007)(11346002)(256004)(486006)(44832011)(476003)(2616005)(446003)(54906003)(316002)(7736002)(305945005)(6116002)(2906002)(3846002)(81156014)(81166006)(102836004)(50226002)(6916009)(386003)(36756003)(8676002)(8936002)(66066001)(2501003);DIR:OUT;SFP:1102;SCL:1;SRVR:MWHPR2201MB1709;H:MWHPR2201MB1277.namprd22.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1;
received-spf: None (protection.outlook.com: wavecomp.com does not designate
 permitted sender hosts)
x-ms-exchange-senderadcheck: 1
x-microsoft-antispam: BCL:0;
x-microsoft-antispam-message-info: yUkh5+LC15kDahG+S2Q8hBXdcqn6LMMPwJUBuifrNN6TJG1DF/VSMOoirPXUo0TLye4OYn6NKLgDQ5BsVhjiPfoaVS0H/UaeUs+lLLZmltWKrA/1yfHJzIMadOlX8yPlhahzjDrTWinDNXsdky3+/IgKcMGrHxHr4x4YJCvHGJSQqoQHIh+82nTHNrutm74ZagmsDp6q/T9MfbKtBIV5OGxhtPoShkGV8bOQbgyOVV6rGy2HWR4JOtUnQooVUsfUlp0vHPQIIQH9JuxFavpjCZnk7Kd7cQVcXVILkDtLg6mZFznz8oJJQoU2L8ZFpgLj6zQPDK/AkRSF9ozfQ46jL4bRI758zS0m/9CwBUbmp8w/6PyOrlrhzJTGTRUZahk4LHdQG5+xJ/pQxN+VjUVwt6vwz0mW6oKarw+YuwrG+gA=
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-OriginatorOrg: mips.com
X-MS-Exchange-CrossTenant-Network-Message-Id: b1826e22-3325-4626-d08f-08d745fb1342
X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2019 23:08:16.1186
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: g058PfiKJbFDaRdEciRO14mvlGYy10cgJ3Qd7roMqvZAvBu0OaAPYFLIM6TPXxoYQ9JtfQA3qiOhpX+TysnMvA==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1709
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

When targeting MIPSr6 or higher make use of a compact branch in LL/SC
loops, preventing the insertion of a delay slot nop that only serves to
waste space.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---

 arch/mips/include/asm/llsc.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/llsc.h b/arch/mips/include/asm/llsc.h
index 9b19f38562ac..d240a4a2d1c4 100644
--- a/arch/mips/include/asm/llsc.h
+++ b/arch/mips/include/asm/llsc.h
@@ -9,6 +9,8 @@
 #ifndef __ASM_LLSC_H
 #define __ASM_LLSC_H
=20
+#include <asm/isa-rev.h>
+
 #if _MIPS_SZLONG =3D=3D 32
 #define SZLONG_LOG 5
 #define SZLONG_MASK 31UL
@@ -32,6 +34,8 @@
  */
 #if R10000_LLSC_WAR
 # define __SC_BEQZ "beqzl	"
+#elif MIPS_ISA_REV >=3D 6
+# define __SC_BEQZ "beqzc	"
 #else
 # define __SC_BEQZ "beqz	"
 #endif
--=20
2.23.0