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Mon, 30 Sep 2019 23:08:14 +0000 From: Paul Burton To: "linux-mips@vger.kernel.org" CC: Huacai Chen , Jiaxun Yang , "linux-kernel@vger.kernel.org" , Paul Burton Subject: [PATCH 00/37] MIPS: barriers & atomics cleanups Thread-Topic: [PATCH 00/37] MIPS: barriers & atomics cleanups Thread-Index: AQHVd+PvZwdGu3aHzU2TPg04oPQmjw== Date: Mon, 30 Sep 2019 23:08:14 +0000 Message-ID: <20190930230806.2940505-1-paul.burton@mips.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BYAPR21CA0006.namprd21.prod.outlook.com (2603:10b6:a03:114::16) To MWHPR2201MB1277.namprd22.prod.outlook.com (2603:10b6:301:18::12) authentication-results: spf=none (sender IP is ) smtp.mailfrom=pburton@wavecomp.com; x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.23.0 x-originating-ip: [12.94.197.246] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 2c5edb22-1b05-4df5-ac13-08d745fb122f x-ms-traffictypediagnostic: MWHPR2201MB1709: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:5797; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: mips.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2c5edb22-1b05-4df5-ac13-08d745fb122f X-MS-Exchange-CrossTenant-originalarrivaltime: 30 Sep 2019 23:08:14.2435 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 463607d3-1db3-40a0-8a29-970c56230104 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: m0WjEEG/SAAL/6n+aC980ifUuzNwJ6qRuMHtnxu3qyjhsAywbHqLd8T3Yez3CL6pmTD+ZzN8F0XzLK4e2LjC9A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR2201MB1709 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series consists of a bunch of cleanups to the way we handle memory barriers (though no changes to the sync instructions we use to implement them) & atomic memory accesses. One major goal was to ensure the Loongson3 LL/SC errata workarounds are applied in a safe manner from within inline-asm & that we can automatically verify the resulting kernel binary looks reasonable. Many patches are cleanups found along the way. Applies atop v5.4-rc1. Paul Burton (37): MIPS: Unify sc beqz definition MIPS: Use compact branch for LL/SC loops on MIPSr6+ MIPS: barrier: Add __SYNC() infrastructure MIPS: barrier: Clean up rmb() & wmb() definitions MIPS: barrier: Clean up __smp_mb() definition MIPS: barrier: Remove fast_mb() Octeon #ifdef'ery MIPS: barrier: Clean up __sync() definition MIPS: barrier: Clean up sync_ginv() MIPS: atomic: Fix whitespace in ATOMIC_OP macros MIPS: atomic: Handle !kernel_uses_llsc first MIPS: atomic: Use one macro to generate 32b & 64b functions MIPS: atomic: Emit Loongson3 sync workarounds within asm MIPS: atomic: Use _atomic barriers in atomic_sub_if_positive() MIPS: atomic: Unify 32b & 64b sub_if_positive MIPS: atomic: Deduplicate 32b & 64b read, set, xchg, cmpxchg MIPS: bitops: Use generic builtin ffs/fls; drop cpu_has_clo_clz MIPS: bitops: Handle !kernel_uses_llsc first MIPS: bitops: Only use ins for bit 16 or higher MIPS: bitops: Use MIPS_ISA_REV, not #ifdefs MIPS: bitops: ins start position is always an immediate MIPS: bitops: Implement test_and_set_bit() in terms of _lock variant MIPS: bitops: Allow immediates in test_and_{set,clear,change}_bit MIPS: bitops: Use the BIT() macro MIPS: bitops: Avoid redundant zero-comparison for non-LLSC MIPS: bitops: Abstract LL/SC loops MIPS: bitops: Use BIT_WORD() & BITS_PER_LONG MIPS: bitops: Emit Loongson3 sync workarounds within asm MIPS: bitops: Use smp_mb__before_atomic in test_* ops MIPS: cmpxchg: Emit Loongson3 sync workarounds within asm MIPS: cmpxchg: Omit redundant barriers for Loongson3 MIPS: futex: Emit Loongson3 sync workarounds within asm MIPS: syscall: Emit Loongson3 sync workarounds within asm MIPS: barrier: Remove loongson_llsc_mb() MIPS: barrier: Make __smp_mb__before_atomic() a no-op for Loongson3 MIPS: genex: Add Loongson3 LL/SC workaround to ejtag_debug_handler MIPS: genex: Don't reload address unnecessarily MIPS: Check Loongson3 LL/SC errata workaround correctness arch/mips/Makefile | 2 +- arch/mips/Makefile.postlink | 10 +- arch/mips/include/asm/atomic.h | 571 ++++++----------- arch/mips/include/asm/barrier.h | 215 +------ arch/mips/include/asm/bitops.h | 593 ++++-------------- arch/mips/include/asm/cmpxchg.h | 59 +- arch/mips/include/asm/cpu-features.h | 10 - arch/mips/include/asm/futex.h | 9 +- arch/mips/include/asm/llsc.h | 19 +- .../asm/mach-malta/cpu-feature-overrides.h | 2 - arch/mips/include/asm/sync.h | 207 ++++++ arch/mips/kernel/genex.S | 6 +- arch/mips/kernel/pm-cps.c | 20 +- arch/mips/kernel/syscall.c | 3 +- arch/mips/lib/bitops.c | 57 +- arch/mips/loongson64/Platform | 2 +- arch/mips/tools/.gitignore | 1 + arch/mips/tools/Makefile | 5 + arch/mips/tools/loongson3-llsc-check.c | 307 +++++++++ 19 files changed, 975 insertions(+), 1123 deletions(-) create mode 100644 arch/mips/include/asm/sync.h create mode 100644 arch/mips/tools/loongson3-llsc-check.c --=20 2.23.0