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From:   Jayachandran Chandrasekharan Nair <jnair@marvell.com>
To:     Bjorn Helgaas <helgaas@kernel.org>
CC:     George Cherian <gcherian@marvell.com>,
        "linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "shannon.zhao@linux.alibaba.com" <shannon.zhao@linux.alibaba.com>,
        George Cherian <gcherian@marvell.com>,
        Vadim Lomovtsev <vlomovtsev@marvell.com>,
        Manish Jaggi <mjaggi@caviumnetworks.com>,
        Robert Richter <rrichter@marvell.com>,
        "Sunil Kovvuri Goutham" <sgoutham@marvell.com>
Subject: Re: [PATCH] PCI: Enhance the ACS quirk for Cavium devices
Thread-Topic: [PATCH] PCI: Enhance the ACS quirk for Cavium devices
Thread-Index: AQHVd+WyQA/rX9/rek2UxMmqvqYW5w==
Date:   Mon, 30 Sep 2019 23:20:50 +0000
Message-ID: <20190930232041.GA22852@dc5-eodlnx05.marvell.com>
References: <20190919024319.GA8792@dc5-eodlnx05.marvell.com>
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On Mon, Sep 30, 2019 at 03:34:10PM -0500, Bjorn Helgaas wrote:
> [+cc Vadim, Manish]

Manish and Vadim are no longer with Cavium, adding Robert for
ThunderX1 and Sunil for Cavium networking processors.

> On Thu, Sep 19, 2019 at 02:43:34AM +0000, George Cherian wrote:
> > Enhance the ACS quirk for Cavium Processors. Add the root port
> > vendor ID's in an array and use the same in match function.
> > For newer devices add the vendor ID's in the array so that the
> > match function is simpler.
> >=20
> > Signed-off-by: George Cherian <george.cherian@marvell.com>
> > ---
> >  drivers/pci/quirks.c | 28 +++++++++++++++++++---------
> >  1 file changed, 19 insertions(+), 9 deletions(-)
> >=20
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 44c4ae1abd00..64deeaddd51c 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -4241,17 +4241,27 @@ static int pci_quirk_amd_sb_acs(struct pci_dev =
*dev, u16 acs_flags)
> >  #endif
> >  }
> > =20
> > +static const u16 pci_quirk_cavium_acs_ids[] =3D {
> > +	/* CN88xx family of devices */
> > +	0xa180, 0xa170,
> > +	/* CN99xx family of devices */
> > +	0xaf84,
> > +	/* CN11xxx family of devices */
> > +	0xb884,
> > +};
> > +
> >  static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
> >  {
> > -	/*
> > -	 * Effectively selects all downstream ports for whole ThunderX 1
> > -	 * family by 0xf800 mask (which represents 8 SoCs), while the lower
> > -	 * bits of device ID are used to indicate which subdevice is used
> > -	 * within the SoC.
> > -	 */
> > -	return (pci_is_pcie(dev) &&
> > -		(pci_pcie_type(dev) =3D=3D PCI_EXP_TYPE_ROOT_PORT) &&
> > -		((dev->device & 0xf800) =3D=3D 0xa000));
> > +	int i;
> > +
> > +	if (!pci_is_pcie(dev) || pci_pcie_type(dev) !=3D PCI_EXP_TYPE_ROOT_PO=
RT)
> > +		return false;
> > +
> > +	for (i =3D 0; i < ARRAY_SIZE(pci_quirk_cavium_acs_ids); i++)
> > +		if (pci_quirk_cavium_acs_ids[i] =3D=3D dev->device)
>=20
> I'm a little skeptical of this because the previous test:
>=20
>   (dev->device & 0xf800) =3D=3D 0xa000
>=20
> could match *many* devices, but of those, the new code only matches two
> (0xa180, 0xa170).
>=20
> And the comment says the new code matches the CN99xx and CN11xxx
> *families*, but it only matches a single device ID for each, which
> makes me think there may be more devices to come.
>=20
> Maybe this is all what you want, but please confirm.

There are only a very few device IDs for root ports, so just listing
them out like this maybe better. The earlier match covered a lot of
ThunderX1 devices, but did not really match the ThunderX2 root ports.

This looks ok for ThunderX2. Sunil & Robert can comment on other
processor families I hope.
=20
> The commit log should be explicit that this adds CN99xx and CN11xxx,
> which previously were not matched.
>=20
> This looks like stable material?
>=20
> > +			return true;
> > +
> > +	return false;
> >  }
> > =20
> >  static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)

JC