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Date:   Tue, 1 Oct 2019 14:40:54 +0200
From:   Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To:     Mika Westerberg <mika.westerberg@linux.intel.com>
Cc:     linux-usb@vger.kernel.org,
        Andreas Noever <andreas.noever@gmail.com>,
        Michael Jamet <michael.jamet@intel.com>,
        Yehezkel Bernat <YehezkelShB@gmail.com>,
        Rajmohan Mani <rajmohan.mani@intel.com>,
        Nicholas Johnson <nicholas.johnson-opensource@outlook.com.au>,
        Lukas Wunner <lukas@wunner.de>,
        Alan Stern <stern@rowland.harvard.edu>,
        Mario.Limonciello@dell.com,
        Anthony Wong <anthony.wong@canonical.com>,
        linux-kernel@vger.kernel.org
Subject: Re: [RFC PATCH 08/22] thunderbolt: Add downstream PCIe port mappings
 for Alpine and Titan Ridge
Message-ID: <20191001124054.GC2954373@kroah.com>
References: <20191001113830.13028-1-mika.westerberg@linux.intel.com>
 <20191001113830.13028-9-mika.westerberg@linux.intel.com>
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On Tue, Oct 01, 2019 at 02:38:16PM +0300, Mika Westerberg wrote:
> In order to keep PCIe hierarchies consistent across hotplugs, add
> hard-coded PCIe downstream port to Thunderbolt port for Alpine Ridge and
> Titan Ridge as well.

Oh, that makes me nervous, how could a hard-coded pcie port ever get set
up incorrectly :)

How do we "know" that this is correct?  Is there any ACPI guarantees
that this "always will be so"?  If not, we all know someone will mess
this up...

> 
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
> ---
>  drivers/thunderbolt/tb.c |  4 +++-
>  drivers/thunderbolt/tb.h | 25 +++++++++++++++++++++++++
>  2 files changed, 28 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c
> index dbbe9afb9fb7..704455a4f763 100644
> --- a/drivers/thunderbolt/tb.c
> +++ b/drivers/thunderbolt/tb.c
> @@ -344,10 +344,12 @@ static struct tb_port *tb_find_pcie_down(struct tb_switch *sw,
>  		 * Hard-coded Thunderbolt port to PCIe down port mapping
>  		 * per controller.
>  		 */
> -		if (tb_switch_is_cr(sw))
> +		if (tb_switch_is_cr(sw) || tb_switch_is_ar(sw))
>  			index = !phy_port ? 6 : 7;
>  		else if (tb_switch_is_fr(sw))
>  			index = !phy_port ? 6 : 8;
> +		else if (tb_switch_is_tr(sw))
> +			index = !phy_port ? 8 : 9;
>  		else
>  			goto out;
>  
> diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h
> index e641dcebd50a..dbab06551eaa 100644
> --- a/drivers/thunderbolt/tb.h
> +++ b/drivers/thunderbolt/tb.h
> @@ -632,6 +632,31 @@ static inline bool tb_switch_is_fr(const struct tb_switch *sw)
>  	}
>  }
>  
> +static inline bool tb_switch_is_ar(const struct tb_switch *sw)

"ar"?  Can you spell it out?

> +{
> +	switch (sw->config.device_id) {
> +	case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE:
> +	case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE:
> +	case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE:
> +	case PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static inline bool tb_switch_is_tr(const struct tb_switch *sw)

Same for "tr" please.

thanks,

greg k-h