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From:   Paul Burton <paul.burton@mips.com>
To:     "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
CC:     Huacai Chen <chenhc@lemote.com>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Paul Burton <pburton@wavecomp.com>
Subject: [PATCH v2 23/36] MIPS: bitops: Avoid redundant zero-comparison for
 non-LLSC
Thread-Topic: [PATCH v2 23/36] MIPS: bitops: Avoid redundant zero-comparison
 for non-LLSC
Thread-Index: AQHVeKKr/ZciCZFEkku5+pQr0Jn66g==
Date:   Tue, 1 Oct 2019 21:53:32 +0000
Message-ID: <20191001215249.4157062-24-paul.burton@mips.com>
References: <20191001215249.4157062-1-paul.burton@mips.com>
In-Reply-To: <20191001215249.4157062-1-paul.burton@mips.com>
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The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already
return a zero or one, so there's no need to perform another comparison
against zero. Move these comparisons into the LLSC paths to avoid the
redundant work.

Signed-off-by: Paul Burton <paul.burton@mips.com>
---

Changes in v2: None

 arch/mips/include/asm/bitops.h | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.=
h
index 0f8ff896e86b..7671db2a7b73 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -264,6 +264,8 @@ static inline int test_and_set_bit_lock(unsigned long n=
r,
 		: "=3D&r" (temp), "+m" (*m), "=3D&r" (res)
 		: "ir" (BIT(bit))
 		: __LLSC_CLOBBER);
+
+		res =3D res !=3D 0;
 	} else {
 		loongson_llsc_mb();
 		do {
@@ -279,12 +281,12 @@ static inline int test_and_set_bit_lock(unsigned long=
 nr,
 			: __LLSC_CLOBBER);
 		} while (unlikely(!res));
=20
-		res =3D temp & BIT(bit);
+		res =3D (temp & BIT(bit)) !=3D 0;
 	}
=20
 	smp_llsc_mb();
=20
-	return res !=3D 0;
+	return res;
 }
=20
 /*
@@ -335,6 +337,8 @@ static inline int test_and_clear_bit(unsigned long nr,
 		: "=3D&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=3D&r" (res)
 		: "ir" (BIT(bit))
 		: __LLSC_CLOBBER);
+
+		res =3D res !=3D 0;
 	} else if ((MIPS_ISA_REV >=3D 2) && __builtin_constant_p(nr)) {
 		loongson_llsc_mb();
 		do {
@@ -363,12 +367,12 @@ static inline int test_and_clear_bit(unsigned long nr=
,
 			: __LLSC_CLOBBER);
 		} while (unlikely(!res));
=20
-		res =3D temp & BIT(bit);
+		res =3D (temp & BIT(bit)) !=3D 0;
 	}
=20
 	smp_llsc_mb();
=20
-	return res !=3D 0;
+	return res;
 }
=20
 /*
@@ -403,6 +407,8 @@ static inline int test_and_change_bit(unsigned long nr,
 		: "=3D&r" (temp), "+" GCC_OFF_SMALL_ASM() (*m), "=3D&r" (res)
 		: "ir" (BIT(bit))
 		: __LLSC_CLOBBER);
+
+		res =3D res !=3D 0;
 	} else {
 		loongson_llsc_mb();
 		do {
@@ -418,12 +424,12 @@ static inline int test_and_change_bit(unsigned long n=
r,
 			: __LLSC_CLOBBER);
 		} while (unlikely(!res));
=20
-		res =3D temp & BIT(bit);
+		res =3D (temp & BIT(bit)) !=3D 0;
 	}
=20
 	smp_llsc_mb();
=20
-	return res !=3D 0;
+	return res;
 }
=20
 #include <asm-generic/bitops/non-atomic.h>
--=20
2.23.0