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[209.132.180.67]) by mx.google.com with ESMTP id u2si9732547ejr.332.2019.10.01.22.55.12; Tue, 01 Oct 2019 22:55:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728735AbfJAWJQ (ORCPT + 99 others); Tue, 1 Oct 2019 18:09:16 -0400 Received: from mail-io1-f67.google.com ([209.85.166.67]:41822 "EHLO mail-io1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728710AbfJAWJP (ORCPT ); Tue, 1 Oct 2019 18:09:15 -0400 Received: by mail-io1-f67.google.com with SMTP id n26so23642972ioj.8; Tue, 01 Oct 2019 15:09:13 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:message-id:date:from:to:cc:subject:references :mime-version:content-disposition:in-reply-to; bh=nlWjCK4JfoFwVHPd1CXSJz1uB7s9TlzfcEVekMEDvj4=; b=bTVUKo9SipbtKo0Zec4iG3wm79rG6S1xFjxhZ9y6nP7YYoSgOkgxdDS3Qp2HPxPMgZ OJLYEUiwImTjlkFoUYUs8Z6gwAjrU+lDypdWLXgUfo2lIppczGnKDSSSM/pOz4fG4020 QZxIdhL9y9DHQXBccSobsU89j/vrc8dcC5lin9wacS3Dxxr5p3Pnbnhjm9snIRrT38S0 MRm8v3O+8vhc8LAmI29XNAhj4EQSiMDA5wG+ldl8Ls7kCOvrCAjXKSur5X1ozApSN6v+ nOsm4MJw0JY2xMfhjDKEBvGlJPXtkIEhyfU3eIoMyXWTc42eoGYggHyAO7wpT1dMUO92 aL/g== X-Gm-Message-State: APjAAAWZ4kr9xcivejLCn+rgm3Rd06wXJVKNJkiQogT9/f59mSGfPhy9 b24DfLiUVQdFAjpE+5sIPeCRHgA= X-Received: by 2002:a92:3bca:: with SMTP id n71mr380086ilh.104.1569967752751; Tue, 01 Oct 2019 15:09:12 -0700 (PDT) Received: from localhost ([2607:fb90:1780:6fbf:9c38:e932:436b:4079]) by smtp.gmail.com with ESMTPSA id o187sm6921932ila.13.2019.10.01.15.09.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 15:09:12 -0700 (PDT) Message-ID: <5d93ce88.1c69fb81.aec64.6b1b@mx.google.com> Date: Tue, 01 Oct 2019 17:09:09 -0500 From: Rob Herring To: Jianxin Pan Cc: Kevin Hilman , linux-amlogic@lists.infradead.org, Zhiqiang Liang , Neil Armstrong , Jerome Brunet , Martin Blumenstingl , linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jian Hu , Hanjie Lin , Victor Wan , Xingyu Chen Subject: Re: [PATCH 1/3] dt-bindings: power: add Amlogic secure power domains bindings References: <1568895064-4116-1-git-send-email-jianxin.pan@amlogic.com> <1568895064-4116-2-git-send-email-jianxin.pan@amlogic.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1568895064-4116-2-git-send-email-jianxin.pan@amlogic.com> X-Mutt-References: <1568895064-4116-2-git-send-email-jianxin.pan@amlogic.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Sep 19, 2019 at 08:11:02AM -0400, Jianxin Pan wrote: > Add the bindings for the Amlogic Secure power domains, controlling the > secure power domains. > > The bindings targets the Amlogic A1 and C1 compatible SoCs, in which the > power domain registers are in secure world. > > Signed-off-by: Jianxin Pan > Signed-off-by: Zhiqiang Liang > --- > .../bindings/power/amlogic,meson-sec-pwrc.yaml | 32 ++++++++++++++++++++++ > include/dt-bindings/power/meson-a1-power.h | 32 ++++++++++++++++++++++ > 2 files changed, 64 insertions(+) > create mode 100644 Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml > create mode 100644 include/dt-bindings/power/meson-a1-power.h > > diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml > new file mode 100644 > index 00000000..327e0d9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml > @@ -0,0 +1,32 @@ > +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +# Copyright (c) 2019 Amlogic, Inc > +# Author: Jianxin Pan > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/power/amlogic,meson-sec-pwrc.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Amlogic Meson Secure Power Domains > + > +maintainers: > + - Jianxin Pan > + > +description: |+ > + A1/C1 series The Secure Power Domains node should be the child of a syscon > + node with the required property. 'a syscon node' is not specific enough. It must be a specific node. > + > +properties: > + compatible: > + enum: > + - amlogic,meson-a1-pwrc > + > +required: > + - compatible > + > +examples: > + - | > + pwrc: power-controller { > + compatible = "amlogic,meson-a1-pwrc"; But why do you need this node? It has no resources. #power-domain-cells needed? > + }; > + > + > diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h > new file mode 100644 > index 00000000..6cf50bf > --- /dev/null > +++ b/include/dt-bindings/power/meson-a1-power.h > @@ -0,0 +1,32 @@ > +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ > +/* > + * Copyright (c) 2019 Amlogic, Inc. > + * Author: Jianxin Pan > + */ > + > +#ifndef _DT_BINDINGS_MESON_A1_POWER_H > +#define _DT_BINDINGS_MESON_A1_POWER_H > + > +#define PWRC_DSPA_ID 8 > +#define PWRC_DSPB_ID 9 > +#define PWRC_UART_ID 10 > +#define PWRC_DMC_ID 11 > +#define PWRC_I2C_ID 12 > +#define PWRC_PSRAM_ID 13 > +#define PWRC_ACODEC_ID 14 > +#define PWRC_AUDIO_ID 15 > +#define PWRC_OTP_ID 16 > +#define PWRC_DMA_ID 17 > +#define PWRC_SD_EMMC_ID 18 > +#define PWRC_RAMA_ID 19 > +#define PWRC_RAMB_ID 20 > +#define PWRC_IR_ID 21 > +#define PWRC_SPICC_ID 22 > +#define PWRC_SPIFC_ID 23 > +#define PWRC_USB_ID 24 > +#define PWRC_NIC_ID 25 > +#define PWRC_PDMIN_ID 26 > +#define PWRC_RSA_ID 27 > +#define PWRC_MAX_ID 28 > + > +#endif > -- > 2.7.4 >