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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a13sm20414018pfg.10.2019.10.01.18.17.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 01 Oct 2019 18:17:06 -0700 (PDT) From: Jeffrey Hugo To: bjorn.andersson@linaro.org Cc: agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, marc.w.gonzalez@free.fr, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jeffrey Hugo Subject: [PATCH v4 2/2] arm64: dts: qcom: msm8998: Add gpucc node Date: Tue, 1 Oct 2019 18:17:02 -0700 Message-Id: <20191002011702.36678-1-jeffrey.l.hugo@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191002011555.36571-1-jeffrey.l.hugo@gmail.com> References: <20191002011555.36571-1-jeffrey.l.hugo@gmail.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add MSM8998 GPU Clock Controller DT node. Signed-off-by: Jeffrey Hugo --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 5a9efd749fa6..896f37c936ee 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -3,6 +3,7 @@ #include #include +#include #include #include #include @@ -951,6 +952,19 @@ #interrupt-cells = <0x2>; }; + gpucc: clock-controller@5065000 { + compatible = "qcom,gpucc-msm8998"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0x05065000 0x9000>; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GPLL0_OUT_MAIN>; + clock-names = "xo", + "gpll0"; + }; + spmi_bus: spmi@800f000 { compatible = "qcom,spmi-pmic-arb"; reg = <0x0800f000 0x1000>, -- 2.17.1