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[209.132.180.67]) by mx.google.com with ESMTP id b44si11255531ede.451.2019.10.02.07.07.00; Wed, 02 Oct 2019 07:07:31 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728033AbfJBOFv (ORCPT + 99 others); Wed, 2 Oct 2019 10:05:51 -0400 Received: from inva020.nxp.com ([92.121.34.13]:50562 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726373AbfJBOFt (ORCPT ); Wed, 2 Oct 2019 10:05:49 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 71E701A0AD9; Wed, 2 Oct 2019 16:05:47 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 657BE1A02D1; Wed, 2 Oct 2019 16:05:47 +0200 (CEST) Received: from fsr-ub1664-121.ea.freescale.net (fsr-ub1664-121.ea.freescale.net [10.171.82.171]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id D13B62060C; Wed, 2 Oct 2019 16:05:46 +0200 (CEST) From: Laurentiu Palcu To: Philipp Zabel , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: agx@sigxcpu.org, l.stach@pengutronix.de, Laurentiu Palcu , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/5] dt-bindings: display: imx: add bindings for DCSS Date: Wed, 2 Oct 2019 17:04:56 +0300 Message-Id: <1570025100-5634-5-git-send-email-laurentiu.palcu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1570025100-5634-1-git-send-email-laurentiu.palcu@nxp.com> References: <1570025100-5634-1-git-send-email-laurentiu.palcu@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add bindings for iMX8MQ Display Controller Subsystem. Signed-off-by: Laurentiu Palcu --- .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 86 ++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml new file mode 100644 index 00000000..efd2494 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: iMX8MQ Display Controller Subsystem (DCSS) + +maintainers: + - Laurentiu Palcu + +description: + + The DCSS (display controller sub system) is used to source up to three + display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10 + image processing capabilities are included to provide a solution capable of + driving next generation high dynamic range displays. + +properties: + compatible: + const: nxp,imx8mq-dcss + + reg: + maxItems: 2 + + interrupts: + maxItems: 3 + items: + - description: Context loader completion and error interrupt + - description: DTG interrupt used to signal context loader trigger time + - description: DTG interrupt for Vblank + + interrupt-names: + maxItems: 3 + items: + - const: ctx_ld + - const: ctxld_kick + - const: vblank + + clocks: + maxItems: 5 + items: + - description: Display APB clock for all peripheral PIO access interfaces + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL + - description: RTRAM clock + - description: Pixel clock, can be driver either by HDMI phy clock or MIPI + - description: DTRC clock, needed by video decompressor + + clock-names: + items: + - const: apb + - const: axi + - const: rtrm + - const: pix + - const: dtrc + + port@0: + type: object + description: A port node pointing to a hdmi_in or mipi_in port node. + +examples: + - | + dcss: display-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>; + interrupt-names = "ctx_ld", "ctxld_kick", "vblank"; + interrupt-parent = <&irqsteer>; + clocks = <&clk 248>, <&clk 247>, <&clk 249>, + <&clk 254>,<&clk 122>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc"; + assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>; + assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>; + assigned-clock-rates = <800000000>, + <400000000>; + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + -- 2.7.4