Received: by 2002:a25:824b:0:0:0:0:0 with SMTP id d11csp1196226ybn; Wed, 2 Oct 2019 12:16:18 -0700 (PDT) X-Google-Smtp-Source: APXvYqxBZijWnQ9Hdq4oNkawyMXaB0xsZc4QZ4gaTjtaNx0cQSaMbTRflE+b1uVCTOaHWhmYp40s X-Received: by 2002:a17:906:698c:: with SMTP id i12mr4476605ejr.260.1570043778874; Wed, 02 Oct 2019 12:16:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1570043778; cv=none; d=google.com; s=arc-20160816; b=g+ErlKkLnNvNvLg+IcKyYzFri8do23UfTWzz8gw2iErp728SgAdNmQYGrEVSqkKP9u 9b4+AE5La9D5TAvTp78xjF2C2jTyP6UQU/W28452/+eyPZMqLy9NlS+gffu3wbhMiuuz ZAQwzeKzoW/6nW8UeupSu0AiWlLSqdnMEg61iE60Of0iFNcRcrC/z5ItdzSHUdGOswxs n9urqO3/kurxL46ZPxtVuhBIDSwe2s97CG6CB/EL8NnXflUIIyo35E26oEK6JBCmFHs5 l1bIlXHl/FwYSQiZ3vyTKwY1Q/C/gX9LCum6AYesnNImQp/FgMwguNY6Y6sSNy0ruoGS JzJA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:in-reply-to:subject:message-id:date:cc:to :from:mime-version:content-transfer-encoding:content-disposition; bh=zuU+ODMM53+H12ugETawOw17YR+bKvCSFHrN70g3RKw=; b=heUK2EyIy9CTf0aMdskr52kgAiR46YIXuMomGni0R5Fd9xRRuH1ljilrHMj/moakOG oVRQIM/UbeFYxO9n0YRCq8ZgaOXicHR4IJDXFN1p0d/EvqAehYVfizrjJrqs5CNrJCcy tjitUI716CD8wz8HlMhDvr9mTPu1Y1IjariZQLNVi1vrzK9gb1cVX0BOqo+nb0l6BVFd JHhEg7Af+kMyYXDGr6fvCCr5gqD4BjlAZLvAB8otzCfOlY+8Q7rFi3kZURwg4xpbv5X/ F25yQwbLZnhV8+7qxR+FoS5jDi5r6sPx1JiLVzCUXfjNJqO1hGzZWxXfaa8FcNUN0C0r SPvw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b33si17496edc.265.2019.10.02.12.15.54; Wed, 02 Oct 2019 12:16:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730244AbfJBTNy (ORCPT + 99 others); Wed, 2 Oct 2019 15:13:54 -0400 Received: from shadbolt.e.decadent.org.uk ([88.96.1.126]:35258 "EHLO shadbolt.e.decadent.org.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729034AbfJBTII (ORCPT ); Wed, 2 Oct 2019 15:08:08 -0400 Received: from [192.168.4.242] (helo=deadeye) by shadbolt.decadent.org.uk with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.89) (envelope-from ) id 1iFjyn-00035R-Ld; Wed, 02 Oct 2019 20:08:05 +0100 Received: from ben by deadeye with local (Exim 4.92.1) (envelope-from ) id 1iFjyn-0003ap-8m; Wed, 02 Oct 2019 20:08:05 +0100 Content-Type: text/plain; charset="UTF-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit MIME-Version: 1.0 From: Ben Hutchings To: linux-kernel@vger.kernel.org, stable@vger.kernel.org CC: akpm@linux-foundation.org, Denis Kirjanov , "Joe Burmeister" , "Greg Kroah-Hartman" Date: Wed, 02 Oct 2019 20:06:51 +0100 Message-ID: X-Mailer: LinuxStableQueue (scripts by bwh) X-Patchwork-Hint: ignore Subject: [PATCH 3.16 13/87] tty: max310x: Fix external crystal register setup In-Reply-To: X-SA-Exim-Connect-IP: 192.168.4.242 X-SA-Exim-Mail-From: ben@decadent.org.uk X-SA-Exim-Scanned: No (on shadbolt.decadent.org.uk); SAEximRunCond expanded to false Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 3.16.75-rc1 review patch. If anyone has any objections, please let me know. ------------------ From: Joe Burmeister commit 5d24f455c182d5116dd5db8e1dc501115ecc9c2c upstream. The datasheet states: Bit 4: ClockEnSet the ClockEn bit high to enable an external clocking (crystal or clock generator at XIN). Set the ClockEn bit to 0 to disable clocking Bit 1: CrystalEnSet the CrystalEn bit high to enable the crystal oscillator. When using an external clock source at XIN, CrystalEn must be set low. The bit 4, MAX310X_CLKSRC_EXTCLK_BIT, should be set and was not. This was required to make the MAX3107 with an external crystal on our board able to send or receive data. Signed-off-by: Joe Burmeister Signed-off-by: Greg Kroah-Hartman Signed-off-by: Ben Hutchings --- drivers/tty/serial/max310x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/tty/serial/max310x.c +++ b/drivers/tty/serial/max310x.c @@ -568,7 +568,7 @@ static int max310x_set_ref_clk(struct ma } /* Configure clock source */ - clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT; + clksrc = MAX310X_CLKSRC_EXTCLK_BIT | (xtal ? MAX310X_CLKSRC_CRYST_BIT : 0); /* Configure PLL */ if (pllcfg) {