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[209.132.180.67]) by mx.google.com with ESMTP id v9si1792874eju.434.2019.10.04.07.21.28; Fri, 04 Oct 2019 07:21:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730258AbfJDOUp (ORCPT + 99 others); Fri, 4 Oct 2019 10:20:45 -0400 Received: from metis.ext.pengutronix.de ([85.220.165.71]:45419 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729638AbfJDOUo (ORCPT ); Fri, 4 Oct 2019 10:20:44 -0400 Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1iGORh-0008UR-Aw; Fri, 04 Oct 2019 16:20:37 +0200 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1iGORg-0004n2-VN; Fri, 04 Oct 2019 16:20:36 +0200 Date: Fri, 4 Oct 2019 16:20:36 +0200 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: Rasmus Villemoes Cc: Thierry Reding , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, Rob Herring , linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/6] pwm: mxs: add support for inverse polarity Message-ID: <20191004142036.apzjf54dlzfah5xl@pengutronix.de> References: <20191004133207.6663-1-linux@rasmusvillemoes.dk> <20191004133207.6663-4-linux@rasmusvillemoes.dk> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20191004133207.6663-4-linux@rasmusvillemoes.dk> User-Agent: NeoMutt/20170113 (1.7.2) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c5 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 04, 2019 at 03:32:04PM +0200, Rasmus Villemoes wrote: > If I'm reading of_pwm_xlate_with_flags() right, existing device trees > that set #pwm-cells = 2 will continue to work. Yes, that's what I expect, too. > Signed-off-by: Rasmus Villemoes > --- > drivers/pwm/pwm-mxs.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) > > diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c > index 5a6835e18fc6..57562221c439 100644 > --- a/drivers/pwm/pwm-mxs.c > +++ b/drivers/pwm/pwm-mxs.c > @@ -25,8 +25,11 @@ > #define PERIOD_PERIOD(p) ((p) & 0xffff) > #define PERIOD_PERIOD_MAX 0x10000 > #define PERIOD_ACTIVE_HIGH (3 << 16) > +#define PERIOD_ACTIVE_LOW (2 << 16) > +#define PERIOD_INACTIVE_HIGH (3 << 18) > #define PERIOD_INACTIVE_LOW (2 << 18) > #define PERIOD_POLARITY_NORMAL (PERIOD_ACTIVE_HIGH | PERIOD_INACTIVE_LOW) > +#define PERIOD_POLARITY_INVERSE (PERIOD_ACTIVE_LOW | PERIOD_INACTIVE_HIGH) > #define PERIOD_CDIV(div) (((div) & 0x7) << 20) > #define PERIOD_CDIV_MAX 8 > > @@ -50,9 +53,7 @@ static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > unsigned int period_cycles, duty_cycles; > unsigned long rate; > unsigned long long c; > - > - if (state->polarity != PWM_POLARITY_NORMAL) > - return -ENOTSUPP; > + unsigned int pol_bits; > > /* > * If the PWM channel is disabled, make sure to turn on the > @@ -91,9 +92,12 @@ static int mxs_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > * only take effect at the beginning of a new period, avoiding > * glitches. > */ > + > + pol_bits = state->polarity == PWM_POLARITY_NORMAL ? > + PERIOD_POLARITY_NORMAL : PERIOD_POLARITY_INVERSE; > writel(duty_cycles << 16, > mxs->base + PWM_ACTIVE0 + pwm->hwpwm * 0x20); > - writel(PERIOD_PERIOD(period_cycles) | PERIOD_POLARITY_NORMAL | PERIOD_CDIV(div), > + writel(PERIOD_PERIOD(period_cycles) | pol_bits | PERIOD_CDIV(div), > mxs->base + PWM_PERIOD0 + pwm->hwpwm * 0x20); Is the avoidance of glitches still true when period changes? I assume that yes, but I wonder if you tested that. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | http://www.pengutronix.de/ |