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[209.85.208.170]) by smtp.gmail.com with ESMTPSA id 202sm1492950ljf.75.2019.10.04.13.26.31 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Oct 2019 13:26:31 -0700 (PDT) Received: by mail-lj1-f170.google.com with SMTP id f5so7751221ljg.8 for ; Fri, 04 Oct 2019 13:26:31 -0700 (PDT) X-Received: by 2002:a2e:2bdb:: with SMTP id r88mr10689784ljr.82.1570220791008; Fri, 04 Oct 2019 13:26:31 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Linus Torvalds Date: Fri, 4 Oct 2019 13:26:15 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [GIT PULL] RISC-V updates for v5.4-rc2 To: Paul Walmsley Cc: linux-riscv@lists.infradead.org, Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Oct 4, 2019 at 10:36 AM Paul Walmsley wrote: > > - Ensure that exclusive-load reservations are terminated after system > call or exception handling. This primarily affects QEMU, which does > not expire load reservations. Grr. Can somebody talk sense to the RISC-V architects? Copying the PowerPC model was broken. PowerPC has now become the absolute worst architecture out there wrt just about any memory ordering issues, and the exclusive reservation is just another example of that. ARMv8 and even alpha got this right, and clear the reservation on return from traps/exceptions. Why did RISC-V copy the power model? (Yeah, I realize that ARM did too originally, but they learnt from their mistakes). Oh well. Linus