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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id h125sm3559380wmf.31.2019.10.09.08.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Oct 2019 08:27:07 -0700 (PDT) From: Vitaly Kuznetsov To: Roman Kagan , Michael Kelley Cc: "kvm\@vger.kernel.org" , Lan Tianyu , Joerg Roedel , "K. Y. Srinivasan" , Haiyang Zhang , Stephen Hemminger , Sasha Levin , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "x86\@kernel.org" , "linux-hyperv\@vger.kernel.org" , "linux-kernel\@vger.kernel.org" Subject: Re: [PATCH v3] x86/hyperv: make vapic support x2apic mode In-Reply-To: <20191009145022.28442-1-rkagan@virtuozzo.com> References: <20191009145022.28442-1-rkagan@virtuozzo.com> Date: Wed, 09 Oct 2019 17:27:06 +0200 Message-ID: <87r23mx7lh.fsf@vitty.brq.redhat.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Roman Kagan writes: > Now that there's Hyper-V IOMMU driver, Linux can switch to x2apic mode > when supported by the vcpus. > > However, the apic access functions for Hyper-V enlightened apic assume > xapic mode only. > > As a result, Linux fails to bring up secondary cpus when run as a guest > in QEMU/KVM with both hv_apic and x2apic enabled. > > According to Michael Kelley, when in x2apic mode, the Hyper-V synthetic > apic MSRs behave exactly the same as the corresponding architectural > x2apic MSRs, so there's no need to override the apic accessors. The > only exception is hv_apic_eoi_write, which benefits from lazy EOI when > available; however, its implementation works for both xapic and x2apic > modes. > > Fixes: 29217a474683 ("iommu/hyper-v: Add Hyper-V stub IOMMU driver") > Fixes: 6b48cb5f8347 ("X86/Hyper-V: Enlighten APIC access") > Cc: stable@vger.kernel.org > Suggested-by: Michael Kelley > Signed-off-by: Roman Kagan > --- > v2 -> v3: > - do not introduce x2apic-capable hv_apic accessors; leave original > x2apic accessors instead > > v1 -> v2: > - add ifdefs to handle !CONFIG_X86_X2APIC > > arch/x86/hyperv/hv_apic.c | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/arch/x86/hyperv/hv_apic.c b/arch/x86/hyperv/hv_apic.c > index 5c056b8aebef..26eeff5bd535 100644 > --- a/arch/x86/hyperv/hv_apic.c > +++ b/arch/x86/hyperv/hv_apic.c > @@ -261,10 +261,19 @@ void __init hv_apic_init(void) > > if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) { > pr_info("Hyper-V: Using MSR based APIC access\n"); This pr_info() becomes a bit misleading in x2apic mode, maybe do something like pr_info("Hyper-V: using Enlightened APIC (%s mode)", x2apic_enabled() ? "x2apic" : "xapic"); > + /* > + * With x2apic, architectural x2apic MSRs are equivalent to the > + * respective synthetic MSRs, so there's no need to override > + * the apic accessors. The only exception is > + * hv_apic_eoi_write, because it benefits from lazy EOI when > + * available, but it works for both xapic and x2apic modes. > + */ > apic_set_eoi_write(hv_apic_eoi_write); > - apic->read = hv_apic_read; > - apic->write = hv_apic_write; > - apic->icr_write = hv_apic_icr_write; > - apic->icr_read = hv_apic_icr_read; > + if (!x2apic_enabled()) { > + apic->read = hv_apic_read; > + apic->write = hv_apic_write; > + apic->icr_write = hv_apic_icr_write; > + apic->icr_read = hv_apic_icr_read; > + } > } > } Reviewed-by: Vitaly Kuznetsov -- Vitaly