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Subject: Re: [PATCH] ARM: dts: zynq: enablement of coresight topology
To:     Michal Simek <michal.simek@xilinx.com>,
        <linux-kernel@vger.kernel.org>, <monstr@monstr.eu>,
        <git@xilinx.com>
CC:     Zumeng Chen <zumeng.chen@windriver.com>,
        Mark Rutland <mark.rutland@arm.com>,
        Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
        Rob Herring <robh+dt@kernel.org>,
        Rob Herring <robh@kernel.org>,
        Rob Herring <robherring2@gmail.com>,
        Steffen Trumtrar <s.trumtrar@pengutronix.de>,
        <devicetree@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <u-boot@lists.denx.de>
References: <a38ab93d870a3b1b341a5c0da14fc7f3d4056684.1570630040.git.michal.simek@xilinx.com>
From:   qwang2 <quanyang.wang@windriver.com>
Message-ID: <eb198b89-3b4a-4090-acc5-db036dd0be69@windriver.com>
Date:   Thu, 10 Oct 2019 15:35:48 +0800
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On 10/9/19 10:07 PM, Michal Simek wrote:
> From: Zumeng Chen <zumeng.chen@windriver.com>
>
> This patch is to build the coresight topology structure of zynq-7000
> series according to the docs of coresight and userguide of zynq-7000.
>
> Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
> Signed-off-by: Quanyang Wang <quanyang.wang@windriver.com>
> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
> ---
>
>   arch/arm/boot/dts/zynq-7000.dtsi | 158 +++++++++++++++++++++++++++++++
>   1 file changed, 158 insertions(+)
>
> diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
> index ca6425ad794c..86430ad76fee 100644
> --- a/arch/arm/boot/dts/zynq-7000.dtsi
> +++ b/arch/arm/boot/dts/zynq-7000.dtsi
> @@ -59,6 +59,40 @@
>   		regulator-always-on;
>   	};
>   
> +	replicator {
> +		compatible = "arm,coresight-static-replicator";
> +		clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> +		clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> +		out-ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			/* replicator output ports */
> +			port@0 {
> +				reg = <0>;
> +				replicator_out_port0: endpoint {
> +					remote-endpoint = <&tpiu_in_port>;
> +				};
> +			};
> +			port@1 {
> +				reg = <1>;
> +				replicator_out_port1: endpoint {
> +					remote-endpoint = <&etb_in_port>;
> +				};
> +			};
> +		};
> +		in-ports {
> +			/* replicator input port */
> +			port {
> +				replicator_in_port0: endpoint {
> +					slave-mode;
> +					remote-endpoint = <&funnel_out_port>;
> +				};
> +			};
> +		};
> +	};
> +
>   	amba: amba {
>   		compatible = "simple-bus";
>   		#address-cells = <1>;
> @@ -365,5 +399,129 @@
>   			reg = <0xf8005000 0x1000>;
>   			timeout-sec = <10>;
>   		};
> +
> +		etb@f8801000 {
> +			compatible = "arm,coresight-etb10", "arm,primecell";
> +			reg = <0xf8801000 0x1000>;
> +			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> +			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			in-ports {
> +				port {
> +					etb_in_port: endpoint {
> +						remote-endpoint = <&replicator_out_port1>;
> +					};
> +				};
> +			};
> +		};
> +
> +		tpiu@f8803000 {
> +			compatible = "arm,coresight-tpiu", "arm,primecell";
> +			reg = <0xf8803000 0x1000>;
> +			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> +			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			in-ports {
> +				port {
> +					tpiu_in_port: endpoint {
> +						remote-endpoint = <&replicator_out_port0>;
> +					};
> +				};
> +			};
> +		};
> +
> +		funnel@f8804000 {
> +			compatible = "arm,coresight-static-funnel", "arm,primecell";
> +			reg = <0xf8804000 0x1000>;
> +			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> +			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +
> +			/* funnel output ports */
> +			out-ports {
> +				port {
> +					funnel_out_port: endpoint {
> +						remote-endpoint =
> +							<&replicator_in_port0>;
> +					};
> +				};
> +			};
> +
> +			in-ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				/* funnel input ports */
> +				port@0 {
> +					reg = <0>;
> +					funnel0_in_port0: endpoint {
> +						remote-endpoint = <&ptm0_out_port>;
> +					};
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +					funnel0_in_port1: endpoint {
> +						remote-endpoint = <&ptm1_out_port>;
> +					};
> +				};
> +
> +				port@2 {
> +					reg = <2>;
> +					funnel0_in_port2: endpoint {
> +					};
> +				};
> +
> +				port@3 {
> +					reg = <3>;
> +					funnel0_in_port3: endpoint {
> +						remote-endpoint = <&itm_out_port>;
> +					};
> +				};
> +				/* The other input ports are not connect to anything */
> +			};
> +		};
> +
> +		/* ITM is not supported by kernel, only leave device node here */
> +		itm@f8805000 {
> +			compatible = "arm,coresight-etm3x", "arm,primecell";

The "arm,coresight-etm3x" shouldn't be the compatible property for ITM. 
Had better remove it.

Thanks,

Quanyang

> +			reg = <0xf8805000 0x1000>;
> +			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> +			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			out-ports {
> +				port {
> +					itm_out_port: endpoint {
> +						remote-endpoint = <&funnel0_in_port3>;
> +					};
> +				};
> +			};
> +		};
> +
> +		ptm@f889c000 {
> +			compatible = "arm,coresight-etm3x", "arm,primecell";
> +			reg = <0xf889c000 0x1000>;
> +			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> +			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			cpu = <&cpu0>;
> +			out-ports {
> +				port {
> +					ptm0_out_port: endpoint {
> +						remote-endpoint = <&funnel0_in_port0>;
> +					};
> +				};
> +			};
> +		};
> +
> +		ptm@f889d000 {
> +			compatible = "arm,coresight-etm3x", "arm,primecell";
> +			reg = <0xf889d000 0x1000>;
> +			clocks = <&clkc 27>, <&clkc 46>, <&clkc 47>;
> +			clock-names = "apb_pclk", "dbg_trc", "dbg_apb";
> +			cpu = <&cpu1>;
> +			out-ports {
> +				port {
> +					ptm1_out_port: endpoint {
> +						remote-endpoint = <&funnel0_in_port1>;
> +					};
> +				};
> +			};
> +		};
>   	};
>   };