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Date:   Tue, 15 Oct 2019 01:16:20 -0700
From:   Christoph Hellwig <hch@infradead.org>
To:     Pankaj Dubey <pankaj.dubey@samsung.com>
Cc:     linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        bhelgaas@google.com, andrew.murray@arm.com,
        lorenzo.pieralisi@arm.com, gustavo.pimentel@synopsys.com,
        jingoohan1@gmail.com, vidyas@nvidia.com,
        Anvesh Salveru <anvesh.s@samsung.com>
Subject: Re: [PATCH v3] PCI: dwc: Add support to add GEN3 related
 equalization quirks
Message-ID: <20191015081620.GA28204@infradead.org>
References: <CGME20191015025933epcas5p1f0891dacc13648559ed8e037e49ee5b1@epcas5p1.samsung.com>
 <1571108362-25962-1-git-send-email-pankaj.dubey@samsung.com>
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On Tue, Oct 15, 2019 at 08:29:22AM +0530, Pankaj Dubey wrote:
> From: Anvesh Salveru <anvesh.s@samsung.com>
> 
> In some platforms, PCIe PHY may have issues which will prevent linkup
> to happen in GEN3 or higher speed. In case equalization fails, link will
> fallback to GEN1.
> 
> DesignWare controller gives flexibility to disable GEN3 equalization
> completely or only phase 2 and 3 of equalization.
> 
> This patch enables the DesignWare driver to disable the PCIe GEN3
> equalization by enabling one of the following quirks:
>  - DWC_EQUALIZATION_DISABLE: To disable GEN3 equalization all phases
>  - DWC_EQ_PHASE_2_3_DISABLE: To disable GEN3 equalization phase 2 & 3
> 
> Platform drivers can set these quirks via "quirk" variable of "dw_pcie"
> struct.

Please submit this together with the changes to the dwc frontend driver
that actually wants to set these quirks.