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[67.185.54.80]) by smtp.gmail.com with ESMTPSA id w11sm21158957pgl.82.2019.10.15.08.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 08:27:23 -0700 (PDT) From: Andrey Smirnov To: linux-arm-kernel@lists.infradead.org Cc: Andrey Smirnov , Fabio Estevam , Chris Healy , Lucas Stach , Shawn Guo , linux-kernel@vger.kernel.org Subject: [PATCH 3/4] arm64: dts: zii-ultra: Add node for accelerometer Date: Tue, 15 Oct 2019 08:26:53 -0700 Message-Id: <20191015152654.26726-3-andrew.smirnov@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191015152654.26726-1-andrew.smirnov@gmail.com> References: <20191015152654.26726-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add I2C node for accelerometer present on both Zest and RMB3 boards. Signed-off-by: Andrey Smirnov Cc: Fabio Estevam Cc: Chris Healy Cc: Lucas Stach Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org, Cc: linux-kernel@vger.kernel.org --- .../boot/dts/freescale/imx8mq-zii-ultra.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index 21eb52341ba8..8395c5a73ba6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -262,6 +262,18 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; + accel@1c { + compatible = "fsl,mma8451"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_accel>; + reg = <0x1c>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "INT2"; + vdd-supply = <®_gen_3p3>; + vddio-supply = <®_gen_3p3>; + }; + ucs1002: charger@32 { compatible = "microchip,ucs1002"; pinctrl-names = "default"; @@ -522,6 +534,12 @@ }; &iomuxc { + pinctrl_accel: accelgrp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41 + >; + }; + pinctrl_fec1: fec1grp { fsl,pins = < MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 -- 2.21.0