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[209.132.180.67]) by mx.google.com with ESMTP id s4si13887777eju.265.2019.10.15.13.29.15; Tue, 15 Oct 2019 13:29:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728551AbfJOQmK (ORCPT + 99 others); Tue, 15 Oct 2019 12:42:10 -0400 Received: from foss.arm.com ([217.140.110.172]:43006 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728557AbfJOQmK (ORCPT ); Tue, 15 Oct 2019 12:42:10 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7DE8B337; Tue, 15 Oct 2019 09:42:09 -0700 (PDT) Received: from lakrids.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 94D923F68E; Tue, 15 Oct 2019 09:42:06 -0700 (PDT) Date: Tue, 15 Oct 2019 17:42:04 +0100 From: Mark Rutland To: Dave Martin Cc: Paul Elliott , Peter Zijlstra , Catalin Marinas , Will Deacon , Yu-cheng Yu , Amit Kachhap , Vincenzo Frascino , linux-arch@vger.kernel.org, Eugene Syromiatnikov , Szabolcs Nagy , "H.J. Lu" , Andrew Jones , Kees Cook , Arnd Bergmann , Jann Horn , Richard Henderson , Kristina =?utf-8?Q?Mart=C5=A1enko?= , Mark Brown , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Florian Weimer , linux-kernel@vger.kernel.org, Sudakshina Das Subject: Re: [PATCH v2 09/12] arm64: traps: Fix inconsistent faulting instruction skipping Message-ID: <20191015164204.GC24604@lakrids.cambridge.arm.com> References: <1570733080-21015-1-git-send-email-Dave.Martin@arm.com> <1570733080-21015-10-git-send-email-Dave.Martin@arm.com> <20191011152453.GF33537@lakrids.cambridge.arm.com> <20191015152108.GX27757@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191015152108.GX27757@arm.com> User-Agent: Mutt/1.11.1+11 (2f07cb52) (2018-12-01) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 15, 2019 at 04:21:09PM +0100, Dave Martin wrote: > On Fri, Oct 11, 2019 at 04:24:53PM +0100, Mark Rutland wrote: > > On Thu, Oct 10, 2019 at 07:44:37PM +0100, Dave Martin wrote: > > > Correct skipping of an instruction on AArch32 works a bit > > > differently from AArch64, mainly due to the different CPSR/PSTATE > > > semantics. > > > > > > There have been various attempts to get this right. Currenty > > > arm64_skip_faulting_instruction() mostly does the right thing, but > > > does not advance the IT state machine for the AArch32 case. > > > > > > arm64_compat_skip_faulting_instruction() handles the IT state > > > machine but is local to traps.c, and porting other code to use it > > > will make a mess since there are some call sites that apply for > > > both the compat and native cases. > > > > > > Since manual instruction skipping implies a trap, it's a relatively > > > slow path. > > > > > > So, make arm64_skip_faulting_instruction() handle both compat and > > > native, and get rid of the arm64_compat_skip_faulting_instruction() > > > special case. > > > > > > Fixes: 32a3e635fb0e ("arm64: compat: Add CNTFRQ trap handler") > > > Fixes: 1f1c014035a8 ("arm64: compat: Add condition code checks and IT advance") > > > Fixes: 6436beeee572 ("arm64: Fix single stepping in kernel traps") > > > Fixes: bd35a4adc413 ("arm64: Port SWP/SWPB emulation support from arm") > > > Signed-off-by: Dave Martin > > > --- > > > arch/arm64/kernel/traps.c | 18 ++++++++---------- > > > 1 file changed, 8 insertions(+), 10 deletions(-) > > > > This looks good to me; it's certainly easier to reason about. > > > > I couldn't spot a place where we do the wrong thing today, given AFAICT > > all the instances in arch/arm64/kernel/armv8_deprecated.c would be > > UNPREDICTABLE within an IT block. > > > > It might be worth calling out an example in the commit message to > > justify the fixes tags. > > IIRC I found no bug here; rather we have pointlessly fragmented code, > so I followed the "if fixing the same bug in multiple places, merge > those places so you need only fix it in one place next time" rule. Sure thing, that makes sense to me. > Since arm64_skip_faulting_instruction() is most of the way to being > generically usable anyway, this series merges all the special-case > handling into it. > > I could add something like > > --8<-- > > This allows this fiddly operation to be maintained in a single > place rather than trying to maintain fragmented versions spread > around arch/arm64. > > -->8-- > > Any good? My big concern is that the commit message reads as a fix, implying that there's an existing correctness bug. I think that simplifying it to make it clearer that it's a cleanup/improvement would be preferable. How about: | arm64: unify native/compat instruction skipping | | Skipping of an instruction on AArch32 works a bit differently from | AArch64, mainly due to the different CPSR/PSTATE semantics. | | Currently arm64_skip_faulting_instruction() is only suitable for | AArch64, and arm64_compat_skip_faulting_instruction() handles the IT | state machine but is local to traps.c. | | Since manual instruction skipping implies a trap, it's a relatively | slow path. | | So, make arm64_skip_faulting_instruction() handle both compat and | native, and get rid of the arm64_compat_skip_faulting_instruction() | special case. | | Signed-off-by: Dave Martin With that, feel free to add: Reviewed-by: Mark Rutland We could even point out that the armv8_deprecated cases are UNPREDICTABLE in an IT block, and correctly emulated either way. Thanks, Mark.