Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Date:   Wed, 16 Oct 2019 10:38:41 +0530
From:   Vinod Koul <vkoul@kernel.org>
To:     Lars-Peter Clausen <lars@metafoo.de>
Cc:     "Ardelean, Alexandru" <alexandru.Ardelean@analog.com>,
        "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
        "alencar.fmce@imbel.gov.br" <alencar.fmce@imbel.gov.br>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] dmaengine: axi-dmac: simple device_config operation
 implemented
Message-ID: <20191016050841.GA2654@vkoul-mobl>
References: <20190913145404.28715-1-alexandru.ardelean@analog.com>
 <20191014070142.GB2654@vkoul-mobl>
 <4384347cc94a54e3fa22790aaa91375afda54e1b.camel@analog.com>
 <20191015104342.GW2654@vkoul-mobl>
 <4428e1fa-1a2a-5a5f-ada8-806078c8da94@metafoo.de>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <4428e1fa-1a2a-5a5f-ada8-806078c8da94@metafoo.de>
User-Agent: Mutt/1.12.1 (2019-06-15)
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

On 15-10-19, 23:06, Lars-Peter Clausen wrote:

> >> This DMA controller is a bit special.
> >> It gets synthesized in FPGA, so the configuration is fixed and cannot be
> >> changed at runtime. Maybe later we would allow/implement this
> >> functionality, but this is a question for my HDL colleagues.
> >>
> >> Two things are done (in this order):
> >> 1. For some paramters, axi_dmac_parse_chan_dt() is used to determine things
> >> from device-tree; as it's an FPGA core, things are synthesized once and
> >> cannot change (yet)
> >> 2. For other parameters, the axi_dmac_detect_caps() is used to guess some
> >> of them at probe time, by doing some reg reads/writes
> > 
> > So the question for you hw folks is how would a controller work with
> > multiple slave devices, do they need to synthesize it everytime?
> > 
> > Rather than that why cant they make the peripheral addresses
> > programmable so that you dont need updating fpga everytime!
> 
> The DMA has a direct connection to the peripheral and the peripheral
> data port is not connected to the general purpose memory interconnect.
> So you can't write to it by an MMIO address and	 there is no address
> that needs to be configured. For an FPGA based design this is quite a
> good solution in terms of resource usage, performance and simplicity. A
> direct connection requires less resources than connection it to the
> central memory interconnect, while at the same time having lower latency
> and not eating up any additional bandwidth on the central memory connect.

thanks for explanation!

> So slave config in this case is a noop and all it can do is verify that
> the requested configuration matches the available configuration.

okay so noop it is!

-- 
~Vinod