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[209.85.128.48]) by smtp.gmail.com with ESMTPSA id z39sm4072162edd.46.2019.10.16.07.54.39 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 16 Oct 2019 07:54:39 -0700 (PDT) Received: by mail-wm1-f48.google.com with SMTP id 5so3284002wmg.0 for ; Wed, 16 Oct 2019 07:54:39 -0700 (PDT) X-Received: by 2002:a1c:a9c5:: with SMTP id s188mr3395636wme.61.1571237678969; Wed, 16 Oct 2019 07:54:38 -0700 (PDT) MIME-Version: 1.0 References: <20191012200524.23512-1-alistair@alistair23.me> <20191016144946.p3tm67vh5lqigndn@gilmour> In-Reply-To: <20191016144946.p3tm67vh5lqigndn@gilmour> From: Chen-Yu Tsai Date: Wed, 16 Oct 2019 22:54:27 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] arm64: dts: sun50i: sopine-baseboard: Expose serial1, serial2 and serial3 To: Maxime Ripard Cc: Alistair Francis , linux-kernel , linux-arm-kernel , alistair23@gmail.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 16, 2019 at 10:49 PM Maxime Ripard wrote: > > Hi, > > On Sat, Oct 12, 2019 at 01:05:24PM -0700, Alistair Francis wrote: > > Follow what the sun50i-a64-pine64.dts does and expose all 5 serial > > connections. > > > > Signed-off-by: Alistair Francis > > --- > > .../allwinner/sun50i-a64-sopine-baseboard.dts | 25 +++++++++++++++++++ > > 1 file changed, 25 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts > > index 124b0b030b28..49c37b21ab36 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts > > @@ -56,6 +56,10 @@ > > aliases { > > ethernet0 = &emac; > > serial0 = &uart0; > > + serial1 = &uart1; > > + serial2 = &uart2; > > + serial3 = &uart3; > > + serial4 = &uart4; > > }; > > > > chosen { > > @@ -280,6 +284,27 @@ > > }; > > }; > > > > +/* On Pi-2 connector */ > > +&uart2 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&uart2_pins>; > > + status = "disabled"; > > +}; > > + > > +/* On Euler connector */ > > +&uart3 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&uart3_pins>; > > + status = "disabled"; > > +}; > > + > > +/* On Euler connector, RTS/CTS optional */ > > +&uart4 { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&uart4_pins>; > > + status = "disabled"; > > +}; > > Since these are all the default muxing, maybe we should just set that > in the DTSI? Maybe not, since people may want to only use RX/TX, and leave the other two pins for GPIO? ChenYu