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[209.132.180.67]) by mx.google.com with ESMTP id e13si2847361edr.429.2019.10.17.22.20.09; Thu, 17 Oct 2019 22:20:33 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391677AbfJPX6A (ORCPT + 99 others); Wed, 16 Oct 2019 19:58:00 -0400 Received: from mail-pf1-f193.google.com ([209.85.210.193]:40959 "EHLO mail-pf1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729897AbfJPX57 (ORCPT ); Wed, 16 Oct 2019 19:57:59 -0400 Received: by mail-pf1-f193.google.com with SMTP id x127so390816pfb.7 for ; Wed, 16 Oct 2019 16:57:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:subject:in-reply-to:cc:from:to:message-id :mime-version:content-transfer-encoding; bh=BbWa1nPh5B2BNvDIpIRryQ0D+zzK6Rg7d2TtU75aidY=; b=W+LN6y5HD1QJcYr65rnXLASVhLny9cMvSf4DdHMgz2tM83K93RR5ISJsAloUGSOMvY RWdd2+oaEsokHHusS+7qi0LXACPMuHcJJYspZxxLxCN+XhhZi9wQEHH58UKb0M0ex/pz T+TSOJgh6iAexrXjoOHnd+pyq33qFCkJoUL/I1Z0AO1H1ZwdhkvJ/IcN89d8Ak7zfyCV hBT5asC6e9UrZh+NI59hUzyGIl09p4R3yHh8qpRLQeta5vOVGkVEdpJUwh4HfgWJF+zx JVtQJAYh5NkdW9HZiiOtbAhiNPC07op/yLkSst/kIvOizFwfNYGTGspuXHsjjvJybETY kcAQ== X-Gm-Message-State: APjAAAWJAj4qWxvyzj081cGqVol7B3TUW4dFwTfCu4j4qUJ/AXv9f+Gu xzp5pXG60Ycb4ie+b3b8jw5oGQ== X-Received: by 2002:a63:575a:: with SMTP id h26mr869322pgm.178.1571270277072; Wed, 16 Oct 2019 16:57:57 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id m9sm304519pjf.11.2019.10.16.16.57.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Oct 2019 16:57:56 -0700 (PDT) Date: Wed, 16 Oct 2019 16:57:56 -0700 (PDT) X-Google-Original-Date: Wed, 16 Oct 2019 16:57:54 PDT (-0700) Subject: Re: [PATCH v2] PCI/MSI: Enable PCI_MSI_IRQ_DOMAIN support for Microblaze In-Reply-To: CC: helgaas@kernel.org, Christoph Hellwig , michal.simek@xilinx.com, linux-kernel@vger.kernel.org, monstr@monstr.eu, git@xilinx.com, kuldeep.dave@xilinx.com, aou@eecs.berkeley.edu, bharat.kumar.gogada@xilinx.com, Greg KH , linux-pci@vger.kernel.org, yamada.masahiro@socionext.com, firoz.khan@linaro.org, Paul Walmsley , linux-riscv@lists.infradead.org, will@kernel.org From: Palmer Dabbelt To: Christoph Hellwig , michal.simek@xilinx.com Message-ID: Mime-Version: 1.0 (MHng) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 14 Oct 2019 22:59:07 PDT (-0700), michal.simek@xilinx.com wrote: > Hi Bjorn, > > On 15. 10. 19 1:23, Bjorn Helgaas wrote: >> On Tue, Oct 08, 2019 at 08:46:52AM -0700, Christoph Hellwig wrote: >>>> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig >>>> index a304f5ea11b9..9d259372fbfd 100644 >>>> --- a/drivers/pci/Kconfig >>>> +++ b/drivers/pci/Kconfig >>>> @@ -52,7 +52,7 @@ config PCI_MSI >>>> If you don't know what to do here, say Y. >>>> >>>> config PCI_MSI_IRQ_DOMAIN >>>> - def_bool ARC || ARM || ARM64 || X86 || RISCV >>>> + def_bool ARC || ARM || ARM64 || X86 || RISCV || MICROBLAZE >>> >>> Can you find out what the actual dependency is so that we can >>> automatically enabled this instead of the weird arch list? >> >> Hi Michal, I'll wait for your response on whether it's feasible to do >> something smarter than listing every arch here. Please ping here or >> post a v3; since I marked this patch "Changed Requested" in patchwork, >> it's fallen off my to-do list. > > I was waiting more for you to comment this. I was expecting that the > same question came last time when RISCV was added. > I am happy to investigate more about it but definitely some your input > would help. Sorry: we usually try to do things the right way but it looks like this got lost in the shuffle. It really doesn't look like there's any architecture-specific code implementation on our end: commit 251a44888183003b0380df184835a2c00bfa39d7 Author: Wesley Terpstra Date: Mon May 20 10:29:26 2019 -0700 riscv: include generic support for MSI irqdomains Some RISC-V systems include PCIe host controllers that support PCIe message-signaled interrupts. For this to work on Linux, we need to enable PCI_MSI_IRQ_DOMAIN and define struct msi_alloc_info. Support for the latter is enabled by including the architecture-generic msi.h include. Signed-off-by: Wesley Terpstra [paul.walmsley@sifive.com: split initial patch into one arch/riscv patch and one drivers/pci patch] Signed-off-by: Paul Walmsley diff --git a/arch/riscv/include/asm/Kbuild b/arch/riscv/include/asm/Kbuild index 1efaeddf1e4b..16970f246860 100644 --- a/arch/riscv/include/asm/Kbuild +++ b/arch/riscv/include/asm/Kbuild @@ -22,6 +22,7 @@ generic-y += kvm_para.h generic-y += local.h generic-y += local64.h generic-y += mm-arch-hooks.h +generic-y += msi.h generic-y += percpu.h generic-y += preempt.h generic-y += sections.h I bet that dropping the architectures and adding msi.h everywhere it's not listed will at least get this building. I'll give diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index a304f5ea11b9..77c1428cd945 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -52,7 +52,7 @@ config PCI_MSI If you don't know what to do here, say Y. config PCI_MSI_IRQ_DOMAIN - def_bool ARC || ARM || ARM64 || X86 || RISCV + def_bool y depends on PCI_MSI select GENERIC_MSI_IRQ_DOMAIN a build everywhere to see what falls out.