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Date:   Thu, 17 Oct 2019 08:31:16 +0100
From:   Lee Jones <lee.jones@linaro.org>
To:     Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc:     Tuowen Zhao <ztuowen@gmail.com>, linux-kernel@vger.kernel.org,
        mika.westerberg@linux.intel.com, acelan.kao@canonical.com,
        mcgrof@kernel.org, davem@davemloft.net
Subject: Re: [PATCH v5 0/4] Fix MTRR bug for intel-lpss-pci
Message-ID: <20191017073116.GM4365@dell>
References: <20191016210629.1005086-1-ztuowen@gmail.com>
 <20191017071409.GC32742@smile.fi.intel.com>
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On Thu, 17 Oct 2019, Andy Shevchenko wrote:

> On Wed, Oct 16, 2019 at 03:06:25PM -0600, Tuowen Zhao wrote:
> > Some BIOS erroneously specifies write-combining BAR for intel-lpss-pci
> > in MTRR. This will cause the system to hang during boot. If possible,
> > this bug could be corrected with a firmware update.
> > 
> > Previous version: https://lkml.org/lkml/2019/10/14/575
> > 
> > Changes from previous version:
> > 
> >  * implement ioremap_uc for sparc64
> >  * split docs changes to not CC stable (doc location moved since 5.3)
> > 
> 
> It forgot to explicitly mention through which tree is supposed to go.
> I think it's MFD one, correct?

To be fair, that's not really up to the submitter to decide.

-- 
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
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