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Date:   Thu, 17 Oct 2019 13:44:10 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     JC Kuo <jckuo@nvidia.com>
Cc:     Rob Herring <robh@kernel.org>,
        Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
        Jon Hunter <jonathanh@nvidia.com>,
        Kishon Vijay Abraham I <kishon@ti.com>,
        linux-tegra@vger.kernel.org,
        Linux USB List <linux-usb@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        devicetree@vger.kernel.org, Nagarjuna Kristam <nkristam@nvidia.com>
Subject: Re: [PATCH v4 3/5] dt-bindings: phy: tegra: Add Tegra194 support
Message-ID: <20191017114410.GD3122066@ulmo>
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On Thu, Oct 17, 2019 at 03:48:52PM +0800, JC Kuo wrote:
> Hi Thierry, Hi Rob, Hi Kishon,
> Please let me know your thoughts of the below implementation.
>=20
> 1. Add a "bool disable_gen2" to "phy->attrs" structure.

phy->attrs is pretty bus agnostic, so adding a USB-specific property
doesn't sound like the right thing to do here.

> 2. In _of_phy_get() of phy-core.c to add the follow to parse a generic pr=
operty.
>=20
> 	phy->attrs.disable_gen2 =3D of_property_read_bool(args.np,
> 							"usb-disable-gen2");
> 3. In individual phy driver, to add SOC/PHY specific programming accordin=
gly.

Could this perhaps be done using the ->set_mode() callback? We don't
currently implement that, but we could implement it and then perhaps use
the submode parameter to distinguish between USB 3.1 Gen 1 and USB 3.1
Gen 2. Perhaps a good mapping would look like this:

	USB 3.1 Gen 1: mode =3D PHY_MODE_USB_HOST_SS, submode =3D 0x0300
	USB 3.1 Gen 2: mode =3D PHY_MODE_USB_HOST_SS, submode =3D 0x0301

The above basically reflects that USB 3.1 Gen 1 is really USB 3.0. This
would also work with other speeds:

	USB 2.0: mode =3D PHY_MODE_USB_HOST_HS, submode =3D 0x0200

etc. I suppose to make this clearer we could add defines for the various
submodes. It seems like submode may be intended to represent one of the
interface modes defined by USBPHY_INTERFACE_MODE_*, but perhaps it can
be repurposed for PHY_MODE_USB_HOST_SS?

Thierry

>=20
> Thanks,
> JC
>=20
> On 10/14/19 9:40 PM, Rob Herring wrote:
> > On Mon, Oct 14, 2019 at 8:17 AM Thierry Reding <thierry.reding@gmail.co=
m> wrote:
> >>
> >> On Wed, Oct 09, 2019 at 06:39:00PM -0500, Rob Herring wrote:
> >>> On Wed, Oct 09, 2019 at 10:43:41AM +0800, JC Kuo wrote:
> >>>> Extend the bindings to cover the set of features found in Tegra194.
> >>>> Note that, technically, there are four more supplies connected to the
> >>>> XUSB pad controller (DVDD_PEX, DVDD_PEX_PLL, HVDD_PEX and HVDD_PEX_P=
LL)
> >>>> , but the power sequencing requirements of Tegra194 require these to=
 be
> >>>> under the control of the PMIC.
> >>>>
> >>>> Tegra194 XUSB PADCTL supports up to USB 3.1 Gen 2 speed, however, it=
 is
> >>>> possible for some platforms have long signal trace that could not
> >>>> provide sufficient electrical environment for Gen 2 speed. To deal w=
ith
> >>>> this, a new device node property "nvidia,disable-gen2" was added to
> >>>> Tegra194 that be used to specifically disable Gen 2 speed for a
> >>>> particular USB 3.0 port so that the port can be limited to Gen 1 spe=
ed
> >>>> and avoid the instability.
> >>>
> >>> I suspect this may be a common issue and we should have a common
> >>> property. Typically, this kind of property is in the controller though
> >>> and supports multiple speed limits. See PCI bindings for inspiration.
> >>
> >> Given that support for gen 2 speeds is dependent on signal trace lengt=
h,
> >> it doesn't really make sense to restrict the whole controller to a giv=
en
> >> speed if only the signal trace for a single port exceeds the limit for
> >> which gen 2 would work.
> >>
> >> Also, the USB PHYs are in a different hardware block than the USB
> >> controller, so this really is a property of the PHY block, not the USB
> >> controller.
> >=20
> > Okay, but still should be common for USB PHYs IMO.
> >=20
> > Rob
> >=20

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