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From:   Abel Vesa <abel.vesa@nxp.com>
To:     Anson Huang <anson.huang@nxp.com>
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Subject: Re: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to
 board DT
Thread-Topic: [PATCH 1/5] arm64: dts: imx8qxp: Move usdhc clocks assignment to
 board DT
Thread-Index: AQHVg8fd9TcILJytHEmYMksBHN4gSadjn8CA
Date:   Sun, 20 Oct 2019 14:35:46 +0000
Message-ID: <20191020143545.we56f4epnbgjr5lw@fsr-ub1664-175>
References: <1571192067-19600-1-git-send-email-Anson.Huang@nxp.com>
In-Reply-To: <1571192067-19600-1-git-send-email-Anson.Huang@nxp.com>
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On 19-10-16 10:14:23, Anson Huang wrote:
> usdhc's clock rate is different according to different devices
> connected, so clock rate assignment should be placed in board
> DT according to different devices connected on each usdhc port.
>=20
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

For the entire patchset:

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>

> ---
>  arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts | 4 ++++
>  arch/arm64/boot/dts/freescale/imx8qxp-mek.dts   | 4 ++++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi      | 6 ------
>  3 files changed, 8 insertions(+), 6 deletions(-)
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64=
/boot/dts/freescale/imx8qxp-ai_ml.dts
> index 91eef97..a3f8cf1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts
> @@ -133,6 +133,8 @@
>  &usdhc1 {
>  	#address-cells =3D <1>;
>  	#size-cells =3D <0>;
> +	assigned-clocks =3D <&clk IMX_CONN_SDHC0_CLK>;
> +	assigned-clock-rates =3D <200000000>;
>  	pinctrl-names =3D "default";
>  	pinctrl-0 =3D <&pinctrl_usdhc1>;
>  	bus-width =3D <4>;
> @@ -149,6 +151,8 @@
> =20
>  /* SD */
>  &usdhc2 {
> +	assigned-clocks =3D <&clk IMX_CONN_SDHC1_CLK>;
> +	assigned-clock-rates =3D <200000000>;
>  	pinctrl-names =3D "default";
>  	pinctrl-0 =3D <&pinctrl_usdhc2>;
>  	bus-width =3D <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/b=
oot/dts/freescale/imx8qxp-mek.dts
> index 88dd9132..d3d26cc 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -137,6 +137,8 @@
>  };
> =20
>  &usdhc1 {
> +	assigned-clocks =3D <&clk IMX_CONN_SDHC0_CLK>;
> +	assigned-clock-rates =3D <200000000>;
>  	pinctrl-names =3D "default";
>  	pinctrl-0 =3D <&pinctrl_usdhc1>;
>  	bus-width =3D <8>;
> @@ -147,6 +149,8 @@
>  };
> =20
>  &usdhc2 {
> +	assigned-clocks =3D <&clk IMX_CONN_SDHC1_CLK>;
> +	assigned-clock-rates =3D <200000000>;
>  	pinctrl-names =3D "default";
>  	pinctrl-0 =3D <&pinctrl_usdhc2>;
>  	bus-width =3D <4>;
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot=
/dts/freescale/imx8qxp.dtsi
> index 2d69f1a..9646a41 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
> @@ -368,8 +368,6 @@
>  				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,
>  				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;
>  			clock-names =3D "ipg", "per", "ahb";
> -			assigned-clocks =3D <&clk IMX_CONN_SDHC0_CLK>;
> -			assigned-clock-rates =3D <200000000>;
>  			power-domains =3D <&pd IMX_SC_R_SDHC_0>;
>  			status =3D "disabled";
>  		};
> @@ -383,8 +381,6 @@
>  				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,
>  				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;
>  			clock-names =3D "ipg", "per", "ahb";
> -			assigned-clocks =3D <&clk IMX_CONN_SDHC1_CLK>;
> -			assigned-clock-rates =3D <200000000>;
>  			power-domains =3D <&pd IMX_SC_R_SDHC_1>;
>  			fsl,tuning-start-tap =3D <20>;
>  			fsl,tuning-step=3D <2>;
> @@ -400,8 +396,6 @@
>  				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,
>  				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;
>  			clock-names =3D "ipg", "per", "ahb";
> -			assigned-clocks =3D <&clk IMX_CONN_SDHC2_CLK>;
> -			assigned-clock-rates =3D <200000000>;
>  			power-domains =3D <&pd IMX_SC_R_SDHC_2>;
>  			status =3D "disabled";
>  		};
> --=20
> 2.7.4
>=20