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[209.132.180.67]) by mx.google.com with ESMTP id a11si1034ejv.310.2019.10.20.19.33.07; Sun, 20 Oct 2019 19:33:32 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726816AbfJUCcw (ORCPT + 99 others); Sun, 20 Oct 2019 22:32:52 -0400 Received: from inva020.nxp.com ([92.121.34.13]:48842 "EHLO inva020.nxp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726726AbfJUCcv (ORCPT ); Sun, 20 Oct 2019 22:32:51 -0400 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id A1C231A04CB; Mon, 21 Oct 2019 04:32:49 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id D22EF1A085F; Mon, 21 Oct 2019 04:32:45 +0200 (CEST) Received: from titan.ap.freescale.net (TITAN.ap.freescale.net [10.192.208.233]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 41597402B4; Mon, 21 Oct 2019 10:32:41 +0800 (SGT) From: Peng Ma To: vkoul@kernel.org Cc: dan.j.williams@intel.com, leoyang.li@nxp.com, k.kozlowski.k@gmail.com, fabio.estevam@nxp.com, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, Peng Ma Subject: [V2] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A platform Date: Mon, 21 Oct 2019 10:21:49 +0800 Message-Id: <20191021022149.37112-1-peng.ma@nxp.com> X-Mailer: git-send-email 2.9.5 X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Our platforms(such as LS1021A, LS1012A, LS1043A, LS1046A, LS1028A) with below registers(CHCFG0 - CHCFG15) of eDMA as follows: *-----------------------------------------------------------* | Offset | OTHERS | LS1028A | |--------------|--------------------|-----------------------| | 0x0 | CHCFG0 | CHCFG3 | |--------------|--------------------|-----------------------| | 0x1 | CHCFG1 | CHCFG2 | |--------------|--------------------|-----------------------| | 0x2 | CHCFG2 | CHCFG1 | |--------------|--------------------|-----------------------| | 0x3 | CHCFG3 | CHCFG0 | |--------------|--------------------|-----------------------| | ... | ...... | ...... | |--------------|--------------------|-----------------------| | 0xC | CHCFG12 | CHCFG15 | |--------------|--------------------|-----------------------| | 0xD | CHCFG13 | CHCFG14 | |--------------|--------------------|-----------------------| | 0xE | CHCFG14 | CHCFG13 | |--------------|--------------------|-----------------------| | 0xF | CHCFG15 | CHCFG12 | *-----------------------------------------------------------* This patch is to improve edma driver to fit LS1028A platform. Signed-off-by: Peng Ma --- Changed for V2: - Explaining what's the "Our platforms" drivers/dma/fsl-edma-common.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index b1a7ca9..611186b 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "fsl-edma-common.h" @@ -42,6 +43,11 @@ #define EDMA_TCD 0x1000 +static struct soc_device_attribute soc_fixup_tuning[] = { + { .family = "QorIQ LS1028A"}, + { }, +}; + static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan) { struct edma_regs *regs = &fsl_chan->edma->regs; @@ -109,10 +115,16 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, u32 ch = fsl_chan->vchan.chan.chan_id; void __iomem *muxaddr; unsigned int chans_per_mux, ch_off; + int endian_diff[4] = {3, 1, -1, -3}; u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs; chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr; ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux; + + if (!fsl_chan->edma->big_endian && + soc_device_match(soc_fixup_tuning)) + ch_off += endian_diff[ch_off % 4]; + muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux]; slot = EDMAMUX_CHCFG_SOURCE(slot); -- 2.9.5