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From:   Leo Li <leoyang.li@nxp.com>
To:     Peng Ma <peng.ma@nxp.com>, "vkoul@kernel.org" <vkoul@kernel.org>,
        Robin Gong <yibin.gong@nxp.com>
CC:     "dan.j.williams@intel.com" <dan.j.williams@intel.com>,
        "k.kozlowski.k@gmail.com" <k.kozlowski.k@gmail.com>,
        Fabio Estevam <fabio.estevam@nxp.com>,
        "dmaengine@vger.kernel.org" <dmaengine@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Peng Ma <peng.ma@nxp.com>
Subject: RE: [V2] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A
 platform
Thread-Topic: [V2] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A
 platform
Thread-Index: AQHVh7fW3WtYHJewrkWzp6KKJUvHnqdlnHdg
Date:   Mon, 21 Oct 2019 21:54:19 +0000
Message-ID: <VE1PR04MB66879FD43E7E7E8A9C157F5D8F690@VE1PR04MB6687.eurprd04.prod.outlook.com>
References: <20191021022149.37112-1-peng.ma@nxp.com>
In-Reply-To: <20191021022149.37112-1-peng.ma@nxp.com>
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> -----Original Message-----
> From: Peng Ma <peng.ma@nxp.com>
> Sent: Sunday, October 20, 2019 9:22 PM
> To: vkoul@kernel.org
> Cc: dan.j.williams@intel.com; Leo Li <leoyang.li@nxp.com>;
> k.kozlowski.k@gmail.com; Fabio Estevam <fabio.estevam@nxp.com>;
> dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; Peng Ma
> <peng.ma@nxp.com>
> Subject: [V2] dmaengine: fsl-edma: Add eDMA support for QorIQ LS1028A
> platform
>=20
> Our platforms(such as LS1021A, LS1012A, LS1043A, LS1046A, LS1028A) with
> below

You only covered QorIQ SoCs, how about the situation for IMX SoCs?

> registers(CHCFG0 - CHCFG15) of eDMA as follows:
> *-----------------------------------------------------------*
> |     Offset   |	OTHERS      |		LS1028A	    |
> |--------------|--------------------|-----------------------|
> |     0x0      |        CHCFG0      |           CHCFG3      |
> |--------------|--------------------|-----------------------|
> |     0x1      |        CHCFG1      |           CHCFG2      |
> |--------------|--------------------|-----------------------|
> |     0x2      |        CHCFG2      |           CHCFG1      |
> |--------------|--------------------|-----------------------|
> |     0x3      |        CHCFG3      |           CHCFG0      |
> |--------------|--------------------|-----------------------|
> |     ...      |        ......      |           ......      |
> |--------------|--------------------|-----------------------|
> |     0xC      |        CHCFG12     |           CHCFG15     |
> |--------------|--------------------|-----------------------|
> |     0xD      |        CHCFG13     |           CHCFG14     |
> |--------------|--------------------|-----------------------|
> |     0xE      |        CHCFG14     |           CHCFG13     |
> |--------------|--------------------|-----------------------|
> |     0xF      |        CHCFG15     |           CHCFG12     |
> *-----------------------------------------------------------*
>=20
> This patch is to improve edma driver to fit LS1028A platform.
>=20
> Signed-off-by: Peng Ma <peng.ma@nxp.com>
> ---
> Changed for V2:
> 	- Explaining what's the "Our platforms"
>=20
>  drivers/dma/fsl-edma-common.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>=20
> diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-
> common.c index b1a7ca9..611186b 100644
> --- a/drivers/dma/fsl-edma-common.c
> +++ b/drivers/dma/fsl-edma-common.c
> @@ -7,6 +7,7 @@
>  #include <linux/module.h>
>  #include <linux/slab.h>
>  #include <linux/dma-mapping.h>
> +#include <linux/sys_soc.h>
>=20
>  #include "fsl-edma-common.h"
>=20
> @@ -42,6 +43,11 @@
>=20
>  #define EDMA_TCD		0x1000
>=20
> +static struct soc_device_attribute soc_fixup_tuning[] =3D {
> +	{ .family =3D "QorIQ LS1028A"},
> +	{ },
> +};
> +
>  static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)  {
>  	struct edma_regs *regs =3D &fsl_chan->edma->regs; @@ -109,10
> +115,16 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
>  	u32 ch =3D fsl_chan->vchan.chan.chan_id;
>  	void __iomem *muxaddr;
>  	unsigned int chans_per_mux, ch_off;
> +	int endian_diff[4] =3D {3, 1, -1, -3};
>  	u32 dmamux_nr =3D fsl_chan->edma->drvdata->dmamuxs;
>=20
>  	chans_per_mux =3D fsl_chan->edma->n_chans / dmamux_nr;
>  	ch_off =3D fsl_chan->vchan.chan.chan_id % chans_per_mux;
> +
> +	if (!fsl_chan->edma->big_endian &&
> +	    soc_device_match(soc_fixup_tuning))
> +		ch_off +=3D endian_diff[ch_off % 4];
> +

This probably is not the best fix now.  There is a new mux_configure32() AP=
I added but it doesn't consider endianness.  How about making it properly t=
aken care of endianness?  And use it to set these registers?

>  	muxaddr =3D fsl_chan->edma->muxbase[ch / chans_per_mux];
>  	slot =3D EDMAMUX_CHCFG_SOURCE(slot);
>=20
> --
> 2.9.5