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Subject: Re: [PATCH v3 6/6] KVM: x86/vPMU: Add lazy mechanism to release
 perf_event per vPMC
To:     Like Xu <like.xu@linux.intel.com>, kvm@vger.kernel.org
Cc:     peterz@infradead.org, like.xu@intel.com,
        linux-kernel@vger.kernel.org, jmattson@google.com,
        sean.j.christopherson@intel.com, wei.w.wang@intel.com,
        kan.liang@intel.com
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 <c17a9d77-2c30-b3c0-4652-57f0b9252f3b@redhat.com>
 <7d46a902-43eb-4693-f481-1c2efd397fbd@linux.intel.com>
From:   Paolo Bonzini <pbonzini@redhat.com>
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Date:   Tue, 22 Oct 2019 16:09:02 +0200
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On 22/10/19 14:00, Like Xu wrote:
>=20
> Second, the structure of pmu->pmc_in_use is in the following format:
>=20
> =C2=A0 Intel: [0 .. INTEL_PMC_MAX_GENERIC-1] <=3D> gp counters
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 [INTEL=
_PMC_IDX_FIXED .. INTEL_PMC_IDX_FIXED + 2] <=3D> fixed
> =C2=A0 AMD:=C2=A0=C2=A0 [0 .. AMD64_NUM_COUNTERS-1] <=3D> gp counters

Sorry---I confused INTEL_PMC_MAX_FIXED and INTEL_PMC_IDX_FIXED.

The patches look good, I'll give them another look since I obviously
wasn't very much awake when reviewing them.

Paolo