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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Viorel Suman <viorel.suman@nxp.com>, Abel Vesa <abel.vesa@nxp.com>,
        Peng Fan <peng.fan@nxp.com>
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Subject: Re: [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for
 clocks
Thread-Topic: [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs
 for clocks
Thread-Index: AQHVRVgHX+vi+LJNg0ufd7EEy7KERw==
Date:   Wed, 23 Oct 2019 08:38:36 +0000
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On 2019-10-23 9:29 AM, Viorel Suman wrote:=0A=
> On Mi, 2019-08-21 at 20:39 +0000, Leonard Crestez wrote:=0A=
>> The audio PLLs should run below 650 mHz so please use 393216000 and=0A=
>> 361267200 instead of 786432000 and 722534400. For the 8mm equivalent see=
=0A=
>> commit 053a4ffe2988 ("clk: imx: imx8mm: fix audio pll setting").=0A=
> =0A=
> Hi Leonard,=0A=
> =0A=
> Audio PLL IP on 8mm and 8mn is different than the Audio PLL IP on 8mq,=0A=
> so the requirement to run below 650 MHZ may not apply to 8mq.=0A=
=0A=
This "max 650mHz" limit is from internal ADD and is also mentioned for =0A=
imx8mq.=0A=
=0A=
Peng: you made the change in our internal tree, can you confirm this =0A=
requirement also applies to 8mq?=0A=
=0A=
Viorel: Is there any impact from 393216000 vs 786432000 on PLL on audio? =
=0A=
As far as I can know this rate goes through various dividers anyway.=0A=
=0A=
--=0A=
Regards,=0A=
Leonard=0A=